[people/ms/u-boot.git] / include / configs / bf537-minotaur.h

/*
 * U-boot - Configuration file for CSP Minotaur board
 *
 * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
 *    Minotaur config, brushed up for official uClinux dist.
 *    Parallel flash support disabled, SPI flash boot command
 *    added ('run flashboot').
 *
 * Flash image map:
 *
 * 0x00000000      u-boot bootstrap
 * 0x00010000      environment
 * 0x00020000      u-boot code
 * 0x00030000      uImage.initramfs
 *
 */

#ifndef __CONFIG_BF537_MINOTAUR_H__
#define __CONFIG_BF537_MINOTAUR_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5


/*
 * Memory Settings
 */
#define CONFIG_MEM_SIZE			32
#define CONFIG_MEM_ADD_WDTH		9

#define CONFIG_EBIU_SDRRC_VAL		0x306
#define CONFIG_EBIU_SDGCTL_VAL		0x91114d

#define CONFIG_EBIU_AMGCTL_VAL		0xFF
#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#endif
#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		bf537-minotaur
#endif

#define CONFIG_SYS_AUTOLOAD	"no"
#define CONFIG_ROOTPATH		"/romfs"


/*
 * Flash Settings
 */
/* We don't have a parallel flash chip there */
#define CONFIG_SYS_NO_FLASH


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_STMICRO


/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR


/*
 * I2C settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI
#define CONFIG_SYS_I2C_SPEED		50000
#define CONFIG_SYS_I2C_SLAVE		0


/*
 * Misc Settings
 */
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_ENV_OVERWRITE	1

#define CONFIG_BAUDRATE		57600
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BFIN_SERIAL

#define CONFIG_PANIC_HANG	1
#define CONFIG_RTC_BFIN		1
#define CONFIG_BOOT_RETRY_TIME	-1
#define CONFIG_LOADS_ECHO		1

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
# define CONFIG_BOOTDELAY	-1
#else
# define CONFIG_BOOTDELAY	5
#endif

#ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#endif

#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SF

#define CONFIG_BOOTCOMMAND	"run ramboot"
#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"

#define BOOT_ENV_SETTINGS \
	"update=tftpboot $(loadaddr) u-boot.ldr;" \
		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
		"sf erase 0 0x30000;" \
		"sf write $(loadaddr) 0 $(filesize)" \
	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
		"bootm 0x1000000\0"
#ifdef CONFIG_BFIN_MAC
# define NETWORK_ENV_SETTINGS \
	"nfsargs=setenv bootargs root=/dev/nfs rw " \
		"nfsroot=$(serverip):$(rootpath)\0" \
	"addip=setenv bootargs $(bootargs) " \
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
		":$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux;" \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux;" \
		"run nfsargs;run addip;bootelf\0"
#else
# define NETWORK_ENV_SETTINGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
	NETWORK_ENV_SETTINGS \
	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
	BOOT_ENV_SETTINGS

#endif
Commit	Line	Data
d7fdc141 MF	1	/*
	2	* U-boot - Configuration file for CSP Minotaur board
	3	*
	4	* Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
	5	* Minotaur config, brushed up for official uClinux dist.
	6	* Parallel flash support disabled, SPI flash boot command
	7	* added ('run flashboot').
	8	*
	9	* Flash image map:
	10	*
	11	* 0x00000000 u-boot bootstrap
	12	* 0x00010000 environment
	13	* 0x00020000 u-boot code
	14	* 0x00030000 uImage.initramfs
	15	*
	16	*/
	17
	18	#ifndef __CONFIG_BF537_MINOTAUR_H__
	19	#define __CONFIG_BF537_MINOTAUR_H__
	20
f348ab85	21	#include <asm/config-pre.h>
d7fdc141 MF	22
	23
	24	/*
	25	* Processor Settings
	26	*/
fbcf8e8c	27	#define CONFIG_BFIN_CPU bf537-0.2
d7fdc141 MF	28	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
	29
	30
	31	/*
	32	* Clock Settings
	33	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	34	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	35	*/
	36	/* CONFIG_CLKIN_HZ is any value in Hz */
	37	#define CONFIG_CLKIN_HZ 25000000
	38	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	39	/* 1 = CLKIN / 2 */
	40	#define CONFIG_CLKIN_HALF 0
	41	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	42	/* 1 = bypass PLL */
	43	#define CONFIG_PLL_BYPASS 0
	44	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	45	/* Values can range from 0-63 (where 0 means 64) */
	46	#define CONFIG_VCO_MULT 20
	47	/* CCLK_DIV controls the core clock divider */
	48	/* Values can be 1, 2, 4, or 8 ONLY */
	49	#define CONFIG_CCLK_DIV 1
	50	/* SCLK_DIV controls the system clock divider */
	51	/* Values can range from 1-15 */
	52	#define CONFIG_SCLK_DIV 5
	53
	54
	55	/*
	56	* Memory Settings
	57	*/
	58	#define CONFIG_MEM_SIZE 32
	59	#define CONFIG_MEM_ADD_WDTH 9
	60
	61	#define CONFIG_EBIU_SDRRC_VAL 0x306
	62	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	63
	64	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	65	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	66	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	67
	68	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	69	#define CONFIG_SYS_MALLOC_LEN (128 << 10)
	70
	71
	72	/*
	73	* Network Settings
	74	*/
	75	#ifndef __ADSPBF534__
	76	#define CONFIG_BFIN_MAC
	77	#define CONFIG_NETCONSOLE 1
d7fdc141 MF	78	#endif
	79	#ifdef CONFIG_BFIN_MAC
	80	#define CONFIG_IPADDR 192.168.0.15
	81	#define CONFIG_NETMASK 255.255.255.0
	82	#define CONFIG_GATEWAYIP 192.168.0.1
	83	#define CONFIG_SERVERIP 192.168.0.2
	84	#define CONFIG_HOSTNAME bf537-minotaur
	85	#endif
	86
	87	#define CONFIG_SYS_AUTOLOAD "no"
8b3637c6	88	#define CONFIG_ROOTPATH "/romfs"
d7fdc141 MF	89
	90
	91	/*
	92	* Flash Settings
	93	*/
	94	/* We don't have a parallel flash chip there */
	95	#define CONFIG_SYS_NO_FLASH
	96
	97
	98	/*
	99	* SPI Settings
	100	*/
	101	#define CONFIG_BFIN_SPI
	102	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	103	#define CONFIG_SF_DEFAULT_SPEED 30000000
d7fdc141 MF	104	#define CONFIG_SPI_FLASH_STMICRO
	105
	106
	107	/*
	108	* Env Storage Settings
	109	*/
	110	#define CONFIG_ENV_IS_IN_SPI_FLASH
	111	#define CONFIG_ENV_OFFSET 0x10000
	112	#define CONFIG_ENV_SIZE 0x10000
	113	#define CONFIG_ENV_SECT_SIZE 0x10000
76d82187	114	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
d7fdc141 MF	115
	116
	117	/*
	118	* I2C settings
	119	*/
c469703b	120	#define CONFIG_SYS_I2C
fea9b69a	121	#define CONFIG_SYS_I2C_ADI
d7fdc141 MF	122	#define CONFIG_SYS_I2C_SPEED 50000
	123	#define CONFIG_SYS_I2C_SLAVE 0
	124
	125
	126	/*
	127	* Misc Settings
	128	*/
	129	#define CONFIG_SYS_LONGHELP 1
	130	#define CONFIG_CMDLINE_EDITING 1
	131	#define CONFIG_ENV_OVERWRITE 1
d7fdc141 MF	132
	133	#define CONFIG_BAUDRATE 57600
	134	#define CONFIG_UART_CONSOLE 0
7a58eb96	135	#define CONFIG_BFIN_SERIAL
d7fdc141 MF	136
	137	#define CONFIG_PANIC_HANG 1
	138	#define CONFIG_RTC_BFIN 1
	139	#define CONFIG_BOOT_RETRY_TIME -1
	140	#define CONFIG_LOADS_ECHO 1
	141
	142	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
	143	# define CONFIG_BOOTDELAY -1
	144	#else
	145	# define CONFIG_BOOTDELAY 5
	146	#endif
	147
d7fdc141 MF	148	#ifdef CONFIG_BFIN_MAC
	149	# define CONFIG_CMD_DHCP
	150	# define CONFIG_CMD_PING
d7fdc141 MF	151	#endif
	152
	153	#define CONFIG_CMD_BOOTLDR
	154	#define CONFIG_CMD_CACHE
	155	#define CONFIG_CMD_DATE
	156	#define CONFIG_CMD_ELF
d7fdc141	157	#define CONFIG_CMD_I2C
d7fdc141 MF	158	#define CONFIG_CMD_SF
	159
	160	#define CONFIG_BOOTCOMMAND "run ramboot"
	161	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
d7fdc141 MF	162
	163	#define BOOT_ENV_SETTINGS \
	164	"update=tftpboot $(loadaddr) u-boot.ldr;" \
5368c55d	165	"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
d7fdc141 MF	166	"sf erase 0 0x30000;" \
	167	"sf write $(loadaddr) 0 $(filesize)" \
	168	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
	169	"bootm 0x1000000\0"
	170	#ifdef CONFIG_BFIN_MAC
	171	# define NETWORK_ENV_SETTINGS \
	172	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	173	"nfsroot=$(serverip):$(rootpath)\0" \
	174	"addip=setenv bootargs $(bootargs) " \
	175	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	176	":$(hostname):eth0:off\0" \
	177	"ramboot=tftpboot $(loadaddr) linux;" \
	178	"run ramargs;run addip;bootelf\0" \
	179	"nfsboot=tftpboot $(loadaddr) linux;" \
	180	"run nfsargs;run addip;bootelf\0"
	181	#else
	182	# define NETWORK_ENV_SETTINGS
	183	#endif
	184	#define CONFIG_EXTRA_ENV_SETTINGS \
	185	NETWORK_ENV_SETTINGS \
	186	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
	187	BOOT_ENV_SETTINGS
	188
d7fdc141	189	#endif