[people/ms/u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-Boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_STAMP_H__
#define __CONFIG_BF537_STAMP_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x306
#define CONFIG_EBIU_SDGCTL_VAL	0x91114d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#endif
#define CONFIG_HOSTNAME		bf537-stamp

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_ALL


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI


/*
 * SPI_MMC Settings
 */
#define CONFIG_MMC_SPI
#ifdef CONFIG_MMC_SPI
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#endif

/*
 * NAND Settings
 */
/* #define CONFIG_NAND_PLAT */
#ifdef CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE		0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
#endif /* CONFIG_NAND_PLAT */

/*
 * CF-CARD IDE-HDD Support
 */

/*
 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 * Strange address mapping Blackfin A13 connects to CF_A0
 */

/* #define CONFIG_BFIN_TRUE_IDE */

/*
 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 * This should be the preferred mode
 */

/* #define CONFIG_BFIN_CF_IDE */

/*
 * Add IDE Disk Drive (HDD) support
 * See example interface here:
 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 */

/* #define CONFIG_BFIN_HDD_IDE */

#if defined(CONFIG_BFIN_CF_IDE) || \
    defined(CONFIG_BFIN_HDD_IDE) || \
    defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
# define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)

#undef  CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */

#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */

#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif

#endif


/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_SYS_POST_HOTKEYS_GPIO	GPIO_PF5
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	10, 11, 12, 13,
#define CONFIG_SYS_POST_FLASH_START	11
#define CONFIG_SYS_POST_FLASH_END	71
#endif

/* These are for board tests */
#if 0
#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
#endif


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
26bf7dec	1	/*
a187559e	2	* U-Boot - Configuration file for BF537 STAMP board
26bf7dec AL	3	*/
26bf7dec AL	4
cf6f469e MF	5	#ifndef __CONFIG_BF537_STAMP_H__
cf6f469e MF	6	#define __CONFIG_BF537_STAMP_H__
26bf7dec	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
26bf7dec	10
cf6f469e MF	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf537-0.2
cf6f469e	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
26bf7dec	16
26bf7dec	17
cf6f469e MF	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
26bf7dec	33	#define CONFIG_VCO_MULT 20
cf6f469e MF	34	/* CCLK_DIV controls the core clock divider */
cf6f469e MF	35	/* Values can be 1, 2, 4, or 8 ONLY */
26bf7dec	36	#define CONFIG_CCLK_DIV 1
cf6f469e MF	37	/* SCLK_DIV controls the system clock divider */
cf6f469e MF	38	/* Values can range from 1-15 */
f82caacc	39	#define CONFIG_SCLK_DIV 4
26bf7dec	40
26bf7dec AL	41
26bf7dec AL	42	/*
cf6f469e	43	* Memory Settings
26bf7dec	44	*/
cf6f469e MF	45	#define CONFIG_MEM_ADD_WDTH 10
	46	#define CONFIG_MEM_SIZE 64
	47
	48	#define CONFIG_EBIU_SDRRC_VAL 0x306
	49	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	52	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	53	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	54
955020c6	55	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
cf6f469e MF	56	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
cf6f469e MF	57
26bf7dec AL	58
	59	/*
	60	* Network Settings
	61	*/
cf6f469e MF	62	#ifndef __ADSPBF534__
	63	#define ADI_CMDS_NETWORK 1
	64	#define CONFIG_BFIN_MAC
	65	#define CONFIG_NETCONSOLE 1
26bf7dec	66	#endif
cf6f469e	67	#define CONFIG_HOSTNAME bf537-stamp
26bf7dec	68
079a136c	69	/*
cf6f469e	70	* Flash Settings
079a136c	71	*/
cf6f469e MF	72	#define CONFIG_FLASH_CFI_DRIVER
	73	#define CONFIG_SYS_FLASH_BASE 0x20000000
	74	#define CONFIG_SYS_FLASH_CFI
	75	#define CONFIG_SYS_FLASH_PROTECTION
	76	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	77	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
	78	#define CONFIG_SYS_MAX_FLASH_SECT 71
079a136c JL	79
079a136c JL	80
ba2351f9	81	/*
cf6f469e	82	* SPI Settings
ba2351f9	83	*/
cf6f469e MF	84	#define CONFIG_BFIN_SPI
cf6f469e MF	85	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	86	#define CONFIG_SF_DEFAULT_SPEED 30000000
f453220c	87	#define CONFIG_SPI_FLASH_ALL
ba2351f9	88
ba2351f9	89
cf6f469e MF	90	/*
	91	* Env Storage Settings
	92	*/
	93	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	94	#define CONFIG_ENV_IS_IN_SPI_FLASH
bc43a8d8	95	#define CONFIG_ENV_OFFSET 0x10000
cf6f469e	96	#define CONFIG_ENV_SIZE 0x2000
bc43a8d8	97	#define CONFIG_ENV_SECT_SIZE 0x10000
26bf7dec	98	#else
cf6f469e MF	99	#define CONFIG_ENV_IS_IN_FLASH
	100	#define CONFIG_ENV_OFFSET 0x4000
	101	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	102	#define CONFIG_ENV_SIZE 0x2000
	103	#define CONFIG_ENV_SECT_SIZE 0x2000
26bf7dec	104	#endif
cf6f469e MF	105	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
cf6f469e MF	106	#define ENV_IS_EMBEDDED
26bf7dec	107	#else
76d82187	108	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
26bf7dec	109	#endif
9ff67e5e MF	110	#ifdef ENV_IS_EMBEDDED
	111	/* WARNING - the following is hand-optimized to fit within
	112	* the sector before the environment sector. If it throws
	113	* an error during compilation remove an object here to get
	114	* it linked after the configuration sector.
	115	*/
	116	# define LDS_BOARD_TEXT \
e2906a59 MY	117	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	118	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	119	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	120	common/env_embedded.o (.text*);
9ff67e5e	121	#endif
6d0f6bcf	122
26bf7dec	123
cf6f469e MF	124	/*
	125	* I2C Settings
	126	*/
c469703b	127	#define CONFIG_SYS_I2C
fea9b69a	128	#define CONFIG_SYS_I2C_ADI
26bf7dec	129
26bf7dec AL	130
26bf7dec AL	131	/*
cf6f469e	132	* SPI_MMC Settings
26bf7dec	133	*/
955020c6 SZ	134	#define CONFIG_MMC_SPI
955020c6 SZ	135	#ifdef CONFIG_MMC_SPI
cf6f469e	136	#define CONFIG_MMC
14dda9df	137	#define CONFIG_GENERIC_MMC
955020c6	138	#endif
26bf7dec AL	139
26bf7dec AL	140	/*
cf6f469e	141	* NAND Settings
26bf7dec	142	*/
cd84423a	143	/* #define CONFIG_NAND_PLAT */
955020c6	144	#ifdef CONFIG_NAND_PLAT
cd84423a	145	#define CONFIG_SYS_NAND_BASE 0x20212000
6d0f6bcf	146	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd84423a MF	147
	148	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	149	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
cd84423a	150	#define BFIN_NAND_WRITE(addr, cmd) \
cf6f469e	151	do { \
cd84423a MF	152	bfin_write8(addr, cmd); \
cd84423a MF	153	SSYNC(); \
26bf7dec AL	154	} while (0)
26bf7dec AL	155
cd84423a MF	156	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
cd84423a MF	157	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
67ceefa7	158	#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
955020c6	159	#endif /* CONFIG_NAND_PLAT */
26bf7dec AL	160
26bf7dec AL	161	/*
cf6f469e	162	* CF-CARD IDE-HDD Support
26bf7dec	163	*/
aa7b248a MH	164
	165	/*
	166	* Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
	167	* Strange address mapping Blackfin A13 connects to CF_A0
	168	*/
	169
	170	/* #define CONFIG_BFIN_TRUE_IDE */
	171
	172	/*
	173	* Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
	174	* This should be the preferred mode
	175	*/
	176
	177	/* #define CONFIG_BFIN_CF_IDE */
	178
	179	/*
	180	* Add IDE Disk Drive (HDD) support
	181	* See example interface here:
	182	* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
	183	*/
	184
	185	/* #define CONFIG_BFIN_HDD_IDE */
26bf7dec	186
cf6f469e MF	187	#if defined(CONFIG_BFIN_CF_IDE) \|\| \
	188	defined(CONFIG_BFIN_HDD_IDE) \|\| \
	189	defined(CONFIG_BFIN_TRUE_IDE)
	190	# define CONFIG_BFIN_IDE 1
	191	# define CONFIG_CMD_IDE
	192	#endif
26bf7dec	193
26bf7dec AL	194	#if defined(CONFIG_BFIN_IDE)
	195
	196	#define CONFIG_DOS_PARTITION 1
	197	/*
	198	* IDE/ATA stuff
	199	*/
	200	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	201	#undef CONFIG_IDE_LED /* no led for ide supported */
	202	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	203
cf6f469e MF	204	#define CONFIG_SYS_IDE_MAXBUS 1
cf6f469e MF	205	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
26bf7dec	206
cf6f469e MF	207	#undef CONFIG_EBIU_AMBCTL1_VAL
cf6f469e MF	208	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
26bf7dec AL	209
	210	#define CONFIG_CF_ATASEL_DIS 0x20311800
	211	#define CONFIG_CF_ATASEL_ENA 0x20311802
	212
	213	#if defined(CONFIG_BFIN_TRUE_IDE)
	214	/*
	215	* Note that these settings aren't for the most part used in include/ata.h
	216	* when all of the ATA registers are setup
	217	*/
6d0f6bcf JCPV	218	#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
6d0f6bcf JCPV	219	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	220	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	221	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	222	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
aa7b248a	223	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
26bf7dec	224
cf6f469e	225	#elif defined(CONFIG_BFIN_CF_IDE)
6d0f6bcf JCPV	226	#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
6d0f6bcf JCPV	227	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	228	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
	229	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
	230	#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
aa7b248a	231	#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
26bf7dec	232
cf6f469e	233	#elif defined(CONFIG_BFIN_HDD_IDE)
6d0f6bcf JCPV	234	#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
6d0f6bcf JCPV	235	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	236	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	237	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	238	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
6d0f6bcf	239	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
26bf7dec AL	240	#undef CONFIG_SCLK_DIV
26bf7dec AL	241	#define CONFIG_SCLK_DIV 8
cf6f469e MF	242	#endif
	243
	244	#endif
26bf7dec	245
cf6f469e MF	246
	247	/*
	248	* Misc Settings
	249	*/
	250	#define CONFIG_MISC_INIT_R
	251	#define CONFIG_RTC_BFIN
	252	#define CONFIG_UART_CONSOLE 0
	253
cf6f469e MF	254	/* Define if want to do post memory test */
	255	#undef CONFIG_POST
	256	#ifdef CONFIG_POST
0fc47444	257	#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
2151374f MF	258	#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	259	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
	260	#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	261	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
	262	#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	263	10, 11, 12, 13,
22f45ce4 MF	264	#define CONFIG_SYS_POST_FLASH_START 11
22f45ce4 MF	265	#define CONFIG_SYS_POST_FLASH_END 71
cf6f469e MF	266	#endif
cf6f469e MF	267
216818c1 MF	268	/* These are for board tests */
	269	#if 0
	270	#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
216818c1 MF	271	#endif
216818c1 MF	272
cf6f469e MF	273
	274	/*
	275	* Pull in common ADI header for remaining command/environment setup
	276	*/
	277	#include <configs/bfin_adi_common.h>
26bf7dec AL	278
26bf7dec AL	279	#endif