[people/ms/u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_STAMP_H__
#define __CONFIG_BF537_STAMP_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x306
#define CONFIG_EBIU_SDGCTL_VAL	0x91114d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#define CONFIG_NET_MULTI	1
#endif
#define CONFIG_HOSTNAME		bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/cpu/traps.o		(.text .text.*); \
	arch/blackfin/cpu/interrupt.o	(.text .text.*); \
	arch/blackfin/cpu/serial.o		(.text .text.*); \
	common/dlmalloc.o		(.text .text.*); \
	lib/crc32.o		(.text .text.*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o		(.text .text.*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_BFIN_TWI_I2C	1
#define CONFIG_HARD_I2C		1


/*
 * SPI_MMC Settings
 */
#define CONFIG_MMC
#define CONFIG_SPI_MMC


/*
 * NAND Settings
 */
/* #define CONFIG_NAND_PLAT */
#define CONFIG_SYS_NAND_BASE		0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3


/*
 * CF-CARD IDE-HDD Support
 */

/*
 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 * Strange address mapping Blackfin A13 connects to CF_A0
 */

/* #define CONFIG_BFIN_TRUE_IDE */

/*
 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 * This should be the preferred mode
 */

/* #define CONFIG_BFIN_CF_IDE */

/*
 * Add IDE Disk Drive (HDD) support
 * See example interface here:
 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 */

/* #define CONFIG_BFIN_HDD_IDE */

#if defined(CONFIG_BFIN_CF_IDE) || \
    defined(CONFIG_BFIN_HDD_IDE) || \
    defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
# define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)

#undef  CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */

#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */

#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif

#endif


/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
#endif
#define CONFIG_SYS_POST_WORD_ADDR	0xFF903FFC

/* These are for board tests */
#if 0
#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
	"autoboot in %d seconds: press space to stop\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR " "
#endif


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
26bf7dec AL	1	/*
	2	* U-boot - Configuration file for BF537 STAMP board
	3	*/
	4
cf6f469e MF	5	#ifndef __CONFIG_BF537_STAMP_H__
cf6f469e MF	6	#define __CONFIG_BF537_STAMP_H__
26bf7dec	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
26bf7dec	10
cf6f469e MF	11	/*
	12	* Processor Settings
	13	*/
cf6f469e	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
26bf7dec	15
26bf7dec	16
cf6f469e MF	17	/*
	18	* Clock Settings
	19	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	20	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	21	*/
	22	/* CONFIG_CLKIN_HZ is any value in Hz */
	23	#define CONFIG_CLKIN_HZ 25000000
	24	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	25	/* 1 = CLKIN / 2 */
	26	#define CONFIG_CLKIN_HALF 0
	27	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	28	/* 1 = bypass PLL */
	29	#define CONFIG_PLL_BYPASS 0
	30	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	31	/* Values can range from 0-63 (where 0 means 64) */
26bf7dec	32	#define CONFIG_VCO_MULT 20
cf6f469e MF	33	/* CCLK_DIV controls the core clock divider */
cf6f469e MF	34	/* Values can be 1, 2, 4, or 8 ONLY */
26bf7dec	35	#define CONFIG_CCLK_DIV 1
cf6f469e MF	36	/* SCLK_DIV controls the system clock divider */
cf6f469e MF	37	/* Values can range from 1-15 */
f82caacc	38	#define CONFIG_SCLK_DIV 4
26bf7dec	39
26bf7dec AL	40
26bf7dec AL	41	/*
cf6f469e	42	* Memory Settings
26bf7dec	43	*/
cf6f469e MF	44	#define CONFIG_MEM_ADD_WDTH 10
	45	#define CONFIG_MEM_SIZE 64
	46
	47	#define CONFIG_EBIU_SDRRC_VAL 0x306
	48	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	49
	50	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	51	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	52	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	53
6f5fd56f	54	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
cf6f469e MF	55	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
cf6f469e MF	56
26bf7dec AL	57
	58	/*
	59	* Network Settings
	60	*/
cf6f469e MF	61	#ifndef __ADSPBF534__
	62	#define ADI_CMDS_NETWORK 1
	63	#define CONFIG_BFIN_MAC
	64	#define CONFIG_NETCONSOLE 1
	65	#define CONFIG_NET_MULTI 1
26bf7dec	66	#endif
cf6f469e	67	#define CONFIG_HOSTNAME bf537-stamp
26bf7dec AL	68	/* Uncomment next line to use fixed MAC address */
26bf7dec AL	69	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
26bf7dec	70
26bf7dec	71
079a136c	72	/*
cf6f469e	73	* Flash Settings
079a136c	74	*/
cf6f469e MF	75	#define CONFIG_FLASH_CFI_DRIVER
	76	#define CONFIG_SYS_FLASH_BASE 0x20000000
	77	#define CONFIG_SYS_FLASH_CFI
	78	#define CONFIG_SYS_FLASH_PROTECTION
	79	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	80	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
	81	#define CONFIG_SYS_MAX_FLASH_SECT 71
079a136c JL	82
079a136c JL	83
ba2351f9	84	/*
cf6f469e	85	* SPI Settings
ba2351f9	86	*/
cf6f469e MF	87	#define CONFIG_BFIN_SPI
cf6f469e MF	88	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	89	#define CONFIG_SF_DEFAULT_SPEED 30000000
cf6f469e	90	#define CONFIG_SPI_FLASH
f453220c	91	#define CONFIG_SPI_FLASH_ALL
ba2351f9	92
ba2351f9	93
cf6f469e MF	94	/*
	95	* Env Storage Settings
	96	*/
	97	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	98	#define CONFIG_ENV_IS_IN_SPI_FLASH
bc43a8d8	99	#define CONFIG_ENV_OFFSET 0x10000
cf6f469e	100	#define CONFIG_ENV_SIZE 0x2000
bc43a8d8	101	#define CONFIG_ENV_SECT_SIZE 0x10000
26bf7dec	102	#else
cf6f469e MF	103	#define CONFIG_ENV_IS_IN_FLASH
	104	#define CONFIG_ENV_OFFSET 0x4000
	105	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	106	#define CONFIG_ENV_SIZE 0x2000
	107	#define CONFIG_ENV_SECT_SIZE 0x2000
26bf7dec	108	#endif
cf6f469e MF	109	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
cf6f469e MF	110	#define ENV_IS_EMBEDDED
26bf7dec	111	#else
76d82187	112	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
26bf7dec	113	#endif
9ff67e5e MF	114	#ifdef ENV_IS_EMBEDDED
	115	/* WARNING - the following is hand-optimized to fit within
	116	* the sector before the environment sector. If it throws
	117	* an error during compilation remove an object here to get
	118	* it linked after the configuration sector.
	119	*/
	120	# define LDS_BOARD_TEXT \
c6fb83d2 PT	121	arch/blackfin/cpu/traps.o (.text .text.*); \
	122	arch/blackfin/cpu/interrupt.o (.text .text.*); \
	123	arch/blackfin/cpu/serial.o (.text .text.*); \
9ff67e5e	124	common/dlmalloc.o (.text .text.*); \
78acc472	125	lib/crc32.o (.text .text.*); \
9ff67e5e MF	126	. = DEFINED(env_offset) ? env_offset : .; \
	127	common/env_embedded.o (.text .text.*);
	128	#endif
6d0f6bcf	129
26bf7dec	130
cf6f469e MF	131	/*
	132	* I2C Settings
	133	*/
	134	#define CONFIG_BFIN_TWI_I2C 1
	135	#define CONFIG_HARD_I2C 1
26bf7dec	136
26bf7dec AL	137
26bf7dec AL	138	/*
cf6f469e	139	* SPI_MMC Settings
26bf7dec	140	*/
cf6f469e	141	#define CONFIG_MMC
ac41c7a0	142	#define CONFIG_SPI_MMC
26bf7dec	143
26bf7dec AL	144
26bf7dec AL	145	/*
cf6f469e	146	* NAND Settings
26bf7dec	147	*/
cd84423a MF	148	/* #define CONFIG_NAND_PLAT */
cd84423a MF	149	#define CONFIG_SYS_NAND_BASE 0x20212000
6d0f6bcf	150	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd84423a MF	151
	152	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	153	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
cd84423a	154	#define BFIN_NAND_WRITE(addr, cmd) \
cf6f469e	155	do { \
cd84423a MF	156	bfin_write8(addr, cmd); \
cd84423a MF	157	SSYNC(); \
26bf7dec AL	158	} while (0)
26bf7dec AL	159
cd84423a MF	160	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
cd84423a MF	161	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
67ceefa7	162	#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
26bf7dec	163
26bf7dec AL	164
26bf7dec AL	165	/*
cf6f469e	166	* CF-CARD IDE-HDD Support
26bf7dec	167	*/
aa7b248a MH	168
	169	/*
	170	* Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
	171	* Strange address mapping Blackfin A13 connects to CF_A0
	172	*/
	173
	174	/* #define CONFIG_BFIN_TRUE_IDE */
	175
	176	/*
	177	* Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
	178	* This should be the preferred mode
	179	*/
	180
	181	/* #define CONFIG_BFIN_CF_IDE */
	182
	183	/*
	184	* Add IDE Disk Drive (HDD) support
	185	* See example interface here:
	186	* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
	187	*/
	188
	189	/* #define CONFIG_BFIN_HDD_IDE */
26bf7dec	190
cf6f469e MF	191	#if defined(CONFIG_BFIN_CF_IDE) \|\| \
	192	defined(CONFIG_BFIN_HDD_IDE) \|\| \
	193	defined(CONFIG_BFIN_TRUE_IDE)
	194	# define CONFIG_BFIN_IDE 1
	195	# define CONFIG_CMD_IDE
	196	#endif
26bf7dec	197
26bf7dec AL	198	#if defined(CONFIG_BFIN_IDE)
	199
	200	#define CONFIG_DOS_PARTITION 1
	201	/*
	202	* IDE/ATA stuff
	203	*/
	204	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	205	#undef CONFIG_IDE_LED /* no led for ide supported */
	206	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	207
cf6f469e MF	208	#define CONFIG_SYS_IDE_MAXBUS 1
cf6f469e MF	209	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
26bf7dec	210
cf6f469e MF	211	#undef CONFIG_EBIU_AMBCTL1_VAL
cf6f469e MF	212	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
26bf7dec AL	213
	214	#define CONFIG_CF_ATASEL_DIS 0x20311800
	215	#define CONFIG_CF_ATASEL_ENA 0x20311802
	216
	217	#if defined(CONFIG_BFIN_TRUE_IDE)
	218	/*
	219	* Note that these settings aren't for the most part used in include/ata.h
	220	* when all of the ATA registers are setup
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
6d0f6bcf JCPV	223	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	224	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	225	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	226	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
aa7b248a	227	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
26bf7dec	228
cf6f469e	229	#elif defined(CONFIG_BFIN_CF_IDE)
6d0f6bcf JCPV	230	#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
6d0f6bcf JCPV	231	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	232	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
	233	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
	234	#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
aa7b248a	235	#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
26bf7dec	236
cf6f469e	237	#elif defined(CONFIG_BFIN_HDD_IDE)
6d0f6bcf JCPV	238	#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
6d0f6bcf JCPV	239	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	240	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	241	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	242	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
6d0f6bcf	243	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
26bf7dec AL	244	#undef CONFIG_SCLK_DIV
26bf7dec AL	245	#define CONFIG_SCLK_DIV 8
cf6f469e MF	246	#endif
	247
	248	#endif
26bf7dec	249
cf6f469e MF	250
	251	/*
	252	* Misc Settings
	253	*/
	254	#define CONFIG_MISC_INIT_R
	255	#define CONFIG_RTC_BFIN
	256	#define CONFIG_UART_CONSOLE 0
	257
cf6f469e MF	258	/* Define if want to do post memory test */
	259	#undef CONFIG_POST
	260	#ifdef CONFIG_POST
	261	#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
	262	#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
	263	#endif
800eb096	264	#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC
cf6f469e	265
216818c1 MF	266	/* These are for board tests */
	267	#if 0
	268	#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
	269	#define CONFIG_AUTOBOOT_KEYED
	270	#define CONFIG_AUTOBOOT_PROMPT \
	271	"autoboot in %d seconds: press space to stop\n", bootdelay
	272	#define CONFIG_AUTOBOOT_STOP_STR " "
	273	#endif
	274
cf6f469e MF	275
	276	/*
	277	* Pull in common ADI header for remaining command/environment setup
	278	*/
	279	#include <configs/bfin_adi_common.h>
26bf7dec AL	280
26bf7dec AL	281	#endif