[people/ms/u-boot.git] / include / configs / bf538f-ezkit.h

/*
 * U-boot - Configuration file for BF538F EZ-Kit Lite board
 */

#ifndef __CONFIG_BF538F_EZKIT_H__
#define __CONFIG_BF538F_EZKIT_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf538-0.4
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	(0x03F6)
#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)

#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | AMBEN_ALL | AMCKEN)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)


/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20310300
#define CONFIG_HOSTNAME		bf538f-ezkit


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
/*
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_ALL
*/

/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#else
#define	CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define	CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI


/*
 * Misc Settings
 */
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
5c45f7ca MF	1	/*
	2	* U-boot - Configuration file for BF538F EZ-Kit Lite board
	3	*/
	4
	5	#ifndef __CONFIG_BF538F_EZKIT_H__
	6	#define __CONFIG_BF538F_EZKIT_H__
	7
f348ab85	8	#include <asm/config-pre.h>
5c45f7ca MF	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf538-0.4
5c45f7ca MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 21
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 4
	40
	41
	42	/*
	43	* Memory Settings
	44	*/
	45	#define CONFIG_MEM_ADD_WDTH 10
	46	#define CONFIG_MEM_SIZE 64
	47
	48	#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
	49	#define CONFIG_EBIU_SDGCTL_VAL (SCTLE \| PSS \| TWR_2 \| TRCD_3 \| TRP_3 \| TRAS_6 \| PASR_ALL \| CL_3)
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO \| AMBEN_ALL \| AMCKEN)
	52	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	53	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	54
	55	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	56	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
	57
	58
	59	/*
	60	* Network Settings
	61	*/
	62	#define ADI_CMDS_NETWORK 1
7194ab80	63	#define CONFIG_SMC91111 1
5c45f7ca MF	64	#define CONFIG_SMC91111_BASE 0x20310300
5c45f7ca MF	65	#define CONFIG_HOSTNAME bf538f-ezkit
5c45f7ca MF	66
	67
	68	/*
	69	* Flash Settings
	70	*/
	71	#define CONFIG_FLASH_CFI_DRIVER
	72	#define CONFIG_SYS_FLASH_BASE 0x20000000
	73	#define CONFIG_SYS_FLASH_CFI
	74	#define CONFIG_SYS_FLASH_PROTECTION
	75	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	76	#define CONFIG_SYS_MAX_FLASH_SECT 71
	77
	78
	79	/*
	80	* SPI Settings
	81	*/
	82	#define CONFIG_BFIN_SPI
	83	#define CONFIG_ENV_SPI_MAX_HZ 30000000
c49eabef	84	/*
afac8b07	85	#define CONFIG_SF_DEFAULT_SPEED 30000000
f453220c	86	#define CONFIG_SPI_FLASH_ALL
c49eabef	87	*/
5c45f7ca MF	88
	89	/*
	90	* Env Storage Settings
	91	*/
	92	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	93	#define CONFIG_ENV_IS_IN_SPI_FLASH
	94	#define CONFIG_ENV_OFFSET 0x4000
	95	#define CONFIG_ENV_SIZE 0x2000
	96	#define CONFIG_ENV_SECT_SIZE 0x2000
	97	#else
	98	#define CONFIG_ENV_IS_IN_FLASH
	99	#define CONFIG_ENV_OFFSET 0x4000
	100	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	101	#define CONFIG_ENV_SIZE 0x2000
	102	#define CONFIG_ENV_SECT_SIZE 0x2000
	103	#endif
	104	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	105	#define ENV_IS_EMBEDDED
	106	#else
76d82187	107	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
5c45f7ca	108	#endif
9ff67e5e MF	109	#ifdef ENV_IS_EMBEDDED
	110	/* WARNING - the following is hand-optimized to fit within
	111	* the sector before the environment sector. If it throws
	112	* an error during compilation remove an object here to get
	113	* it linked after the configuration sector.
	114	*/
	115	# define LDS_BOARD_TEXT \
e2906a59 MY	116	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	117	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	118	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	119	common/env_embedded.o (.text*);
9ff67e5e	120	#endif
5c45f7ca MF	121
	122
	123	/*
	124	* I2C Settings
	125	*/
c469703b	126	#define CONFIG_SYS_I2C
fea9b69a	127	#define CONFIG_SYS_I2C_ADI
5c45f7ca MF	128
	129
	130	/*
	131	* Misc Settings
	132	*/
	133	#define CONFIG_RTC_BFIN
	134	#define CONFIG_UART_CONSOLE 0
5c45f7ca MF	135
	136	/*
	137	* Pull in common ADI header for remaining command/environment setup
	138	*/
	139	#include <configs/bfin_adi_common.h>
	140
5c45f7ca	141	#endif