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Commit | Line | Data |
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76d21803 MF |
1 | /* |
2 | * U-boot - Configuration file for BF548 STAMP board | |
3 | */ | |
4 | ||
5 | #ifndef __CONFIG_BF548_EZKIT_H__ | |
6 | #define __CONFIG_BF548_EZKIT_H__ | |
7 | ||
f348ab85 | 8 | #include <asm/config-pre.h> |
76d21803 MF |
9 | |
10 | ||
11 | /* | |
12 | * Processor Settings | |
13 | */ | |
fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf548-0.0 |
76d21803 MF |
15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
16 | ||
17 | ||
18 | /* | |
19 | * Clock Settings | |
20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
22 | */ | |
23 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
24 | #define CONFIG_CLKIN_HZ 25000000 | |
25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
26 | /* 1 = CLKIN / 2 */ | |
27 | #define CONFIG_CLKIN_HALF 0 | |
28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
29 | /* 1 = bypass PLL */ | |
30 | #define CONFIG_PLL_BYPASS 0 | |
31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
32 | /* Values can range from 0-63 (where 0 means 64) */ | |
33 | #define CONFIG_VCO_MULT 21 | |
34 | /* CCLK_DIV controls the core clock divider */ | |
35 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
36 | #define CONFIG_CCLK_DIV 1 | |
37 | /* SCLK_DIV controls the system clock divider */ | |
38 | /* Values can range from 1-15 */ | |
39 | #define CONFIG_SCLK_DIV 4 | |
40 | ||
41 | ||
42 | /* | |
43 | * Memory Settings | |
44 | */ | |
45 | #define CONFIG_MEM_ADD_WDTH 10 | |
46 | #define CONFIG_MEM_SIZE 64 | |
47 | ||
48 | #define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE | |
49 | #define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 | |
50 | #define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 | |
51 | ||
52 | /* Default EZ-Kit bank mapping: | |
53 | * Async Bank 0 - 32MB Burst Flash | |
54 | * Async Bank 1 - Ethernet | |
55 | * Async Bank 2 - Nothing | |
56 | * Async Bank 3 - Nothing | |
57 | */ | |
58 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF | |
59 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 | |
60 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 | |
61 | #define CONFIG_EBIU_FCTL_VAL (BCLK_4) | |
62 | #define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) | |
63 | ||
fea63e2a | 64 | #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) |
76d21803 MF |
65 | #define CONFIG_SYS_MALLOC_LEN (768 * 1024) |
66 | ||
67 | ||
68 | /* | |
69 | * Network Settings | |
70 | */ | |
71 | #define ADI_CMDS_NETWORK 1 | |
736fead8 BW |
72 | #define CONFIG_SMC911X 1 |
73 | #define CONFIG_SMC911X_BASE 0x24000000 | |
74 | #define CONFIG_SMC911X_16_BIT | |
76d21803 MF |
75 | #define CONFIG_HOSTNAME bf548-ezkit |
76 | /* Uncomment next line to use fixed MAC address */ | |
77 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ | |
78 | ||
79 | ||
80 | /* | |
81 | * Flash Settings | |
82 | */ | |
83 | #define CONFIG_FLASH_CFI_DRIVER | |
84 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
85 | #define CONFIG_SYS_FLASH_CFI | |
86 | #define CONFIG_SYS_FLASH_PROTECTION | |
87 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
88 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
89 | ||
90 | ||
91 | /* | |
92 | * SPI Settings | |
93 | */ | |
94 | #define CONFIG_BFIN_SPI | |
95 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
afac8b07 | 96 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
76d21803 MF |
97 | #define CONFIG_SPI_FLASH |
98 | #define CONFIG_SPI_FLASH_STMICRO | |
99 | ||
100 | ||
101 | /* | |
102 | * Env Storage Settings | |
103 | */ | |
104 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) | |
105 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
106 | #define CONFIG_ENV_OFFSET 0x10000 | |
107 | #define CONFIG_ENV_SIZE 0x2000 | |
108 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
76d82187 | 109 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
76d21803 MF |
110 | #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
111 | #define CONFIG_ENV_IS_IN_NAND | |
d413dbc9 | 112 | #define CONFIG_ENV_OFFSET 0x60000 |
76d21803 MF |
113 | #define CONFIG_ENV_SIZE 0x20000 |
114 | #else | |
1b48f126 | 115 | /* The BF548-EZKIT uses a top boot flash */ |
76d21803 | 116 | #define CONFIG_ENV_IS_IN_FLASH 1 |
1b48f126 MF |
117 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
118 | #define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE) | |
119 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
120 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
76d21803 MF |
121 | #endif |
122 | ||
76d21803 MF |
123 | /* |
124 | * NAND Settings | |
125 | */ | |
76d21803 | 126 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
e0ae433e BL |
127 | #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
128 | #define CONFIG_BFIN_NFC_BOOTROM_ECC | |
76d21803 | 129 | #define CONFIG_DRIVER_NAND_BFIN |
e0ae433e BL |
130 | #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
131 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
132 | #endif | |
76d21803 MF |
133 | |
134 | /* | |
135 | * I2C Settings | |
136 | */ | |
c469703b | 137 | #define CONFIG_SYS_I2C |
fea9b69a | 138 | #define CONFIG_SYS_I2C_ADI |
76d21803 MF |
139 | |
140 | ||
141 | /* | |
142 | * SATA | |
143 | */ | |
144 | #if !defined(__ADSPBF544__) | |
145 | #define CONFIG_LIBATA | |
146 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
147 | #define CONFIG_LBA48 | |
148 | #define CONFIG_PATA_BFIN | |
149 | #define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800 | |
150 | #define CONFIG_BFIN_ATA_MODE XFER_PIO_4 | |
151 | #endif | |
152 | ||
153 | ||
154 | /* | |
155 | * SDH Settings | |
156 | */ | |
157 | #if !defined(__ADSPBF544__) | |
e54c8209 | 158 | #define CONFIG_GENERIC_MMC |
76d21803 MF |
159 | #define CONFIG_MMC |
160 | #define CONFIG_BFIN_SDH | |
161 | #endif | |
162 | ||
163 | ||
164 | /* | |
165 | * USB Settings | |
166 | */ | |
167 | #if !defined(__ADSPBF544__) | |
168 | #define CONFIG_USB | |
169 | #define CONFIG_MUSB_HCD | |
170 | #define CONFIG_USB_BLACKFIN | |
171 | #define CONFIG_USB_STORAGE | |
172 | #define CONFIG_MUSB_TIMEOUT 100000 | |
173 | #endif | |
174 | ||
175 | ||
176 | /* | |
177 | * Misc Settings | |
178 | */ | |
179 | #define CONFIG_BOARD_EARLY_INIT_F | |
58d7570c | 180 | #define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 )) |
76d21803 MF |
181 | #define CONFIG_RTC_BFIN |
182 | #define CONFIG_UART_CONSOLE 1 | |
abaa5ba4 | 183 | #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000 |
76d21803 | 184 | |
da34aae5 SZ |
185 | #define CONFIG_ADI_GPIO2 |
186 | ||
e0ae433e BL |
187 | #undef CONFIG_VIDEO |
188 | #ifdef CONFIG_VIDEO | |
189 | #define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h > | |
190 | #define CONFIG_DEB_DMA_URGENT | |
76d21803 MF |
191 | #endif |
192 | ||
193 | /* Define if want to do post memory test */ | |
194 | #undef CONFIG_POST | |
195 | #ifdef CONFIG_POST | |
2151374f MF |
196 | #define CONFIG_POST_BSPEC1_GPIO_LEDS \ |
197 | GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11, | |
198 | #define CONFIG_POST_BSPEC2_GPIO_BUTTONS \ | |
199 | GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11 | |
200 | #define CONFIG_POST_BSPEC2_GPIO_NAMES \ | |
201 | 13, 12, 11, 10, | |
22f45ce4 MF |
202 | #define CONFIG_SYS_POST_FLASH_START 10 |
203 | #define CONFIG_SYS_POST_FLASH_END 127 | |
76d21803 MF |
204 | #endif |
205 | ||
206 | ||
207 | /* | |
208 | * Pull in common ADI header for remaining command/environment setup | |
209 | */ | |
210 | #include <configs/bfin_adi_common.h> | |
211 | ||
76d21803 | 212 | #endif |