[people/ms/u-boot.git] / include / configs / bf561-ezkit.h

/*
 * U-boot - Configuration file for BF561 EZKIT board
 */

#ifndef __CONFIG_EZKIT561_H__
#define __CONFIG_EZKIT561_H__

#include <asm/blackfin-config-pre.h>

#define CFG_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_BAUDRATE		57600
/* Set default serial console for bf537 */
#define CONFIG_UART_CONSOLE	0
#define CONFIG_EZKIT561		1
#define CONFIG_BOOTDELAY	5

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/*
 * Board settings
 */
#define CONFIG_DRIVER_SMC91111	1
#define CONFIG_SMC91111_BASE	0x2C010300
#define CONFIG_ASYNC_EBIU_BASE	CONFIG_SMC91111_BASE & ~(4*1024*1024)
#define CONFIG_SMC_USE_32_BIT	1
#define CONFIG_MISC_INIT_R	1

/*
 * Clock settings
 */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		30000000
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
/*						 1=bypass PLL	*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT		20
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV		1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV		5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD		2
#define CONFIG_SPI_BAUD_INITBLOCK	4

/*
 * Network settings
 */
#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		ezkit561
#define CONFIG_ROOTPATH		/arm-cross-build/BF561/uClinux-dist/romfs
#endif				/* CONFIG_DRIVER_SMC91111 */

/*
 * Flash settings
 */

#define CFG_FLASH_CFI		/* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET
#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_FLASH_BASE		0x20000000
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
#define CFG_ENV_ADDR		0x20020000
#define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK	0
#define CFG_JFFS2_NUM_BANKS	1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR	8

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH		9	/* 8, 9, 10, 11    */
#define CONFIG_MEM_MT48LC16M16A2TG_75	1

#define	CFG_SDRAM_BASE		0x00000000
#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)

#define CFG_MEMTEST_START	0x0	/* memtest works on */
#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */

#define	CONFIG_LOADADDR		0x01000000	/* default load address */
#define CFG_LOAD_ADDR		CONFIG_LOADADDR
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)

#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)

#define CFG_GBL_DATA_SIZE	0x4000
#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
#endif

/*
 * Command settings
 */

#define CFG_AUTOLOAD	"no"	/* rarpb, bootp, dhcp commands will	*/
				/* only perform a configuration		*/
				/* lookup from the BOOTP/DHCP server	*/
				/* but not try to load any image	*/
				/* using TFTP				*/
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, */
					/* currently its disabled */
#define CONFIG_BOOTCOMMAND	"run ramboot"
#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"

#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):"	\
		"$(rootpath) console=ttyBF0,57600\0"			\
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):"	\
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0"	\
	"ramboot=tftpboot $(loadaddr) linux; "				\
		"run ramargs; run addip; bootelf\0"			\
	"nfsboot=tftpboot $(loadaddr) linux; "				\
		"run nfsargs; run addip; bootelf\0"			\
	"update=tftpboot $(loadaddr) u-boot.bin; "			\
		"protect off 0x20000000 0x2003FFFF; "			\
		"erase 0x20000000 0x2003FFFF; "				\
		"cp.b $(loadaddr) 0x20000000 $(filesize)\0"		\
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	 \
	"flashboot=bootm 0x20100000\0"					\
	""
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2

#if defined(CONFIG_DRIVER_SMC91111)
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#endif

/*
 * Console settings
 */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size */
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
#endif
#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_LOADS_ECHO	1

/*
 * Miscellaneous configurable options
 */
#define	CFG_HZ			1000		/* decrementer freq: 10 ms ticks */
#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */

/*
 * FLASH organization and environment definitions
 */
#define CONFIG_EBIU_SDRRC_VAL  0x306
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
#define CONFIG_EBIU_SDBCTL_VAL 0x15

#define CONFIG_EBIU_AMGCTL_VAL		0x3F
#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0

#include <asm/blackfin-config-post.h>

#endif				/* __CONFIG_EZKIT561_H__ */
Commit	Line	Data
65458987 AL	1	/*
	2	* U-boot - Configuration file for BF561 EZKIT board
	3	*/
	4
	5	#ifndef __CONFIG_EZKIT561_H__
	6	#define __CONFIG_EZKIT561_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
65458987 AL	10	#define CFG_LONGHELP 1
	11	#define CONFIG_CMDLINE_EDITING 1
	12	#define CONFIG_BAUDRATE 57600
	13	/* Set default serial console for bf537 */
	14	#define CONFIG_UART_CONSOLE 0
	15	#define CONFIG_EZKIT561 1
	16	#define CONFIG_BOOTDELAY 5
	17
	18	#define CONFIG_PANIC_HANG 1
	19
f7ce12cb	20	#define CONFIG_BFIN_CPU bf561-0.3
9171fc81	21	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
65458987 AL	22
	23	/* This sets the default state of the cache on U-Boot's boot */
	24	#define CONFIG_ICACHE_ON
	25	#define CONFIG_DCACHE_ON
	26
65458987 AL	27	/*
	28	* Board settings
	29	*/
	30	#define CONFIG_DRIVER_SMC91111 1
	31	#define CONFIG_SMC91111_BASE 0x2C010300
	32	#define CONFIG_ASYNC_EBIU_BASE CONFIG_SMC91111_BASE & ~(410241024)
	33	#define CONFIG_SMC_USE_32_BIT 1
	34	#define CONFIG_MISC_INIT_R 1
	35
	36	/*
	37	* Clock settings
	38	*/
	39
	40	/* CONFIG_CLKIN_HZ is any value in Hz */
	41	#define CONFIG_CLKIN_HZ 30000000
	42	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	43	/* 1=CLKIN/2 */
	44	#define CONFIG_CLKIN_HALF 0
	45	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	46	/* 1=bypass PLL */
	47	#define CONFIG_PLL_BYPASS 0
	48	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is */
	49	/* Values can range from 1-64 */
	50	#define CONFIG_VCO_MULT 20
	51	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	52	/* Values can be 1, 2, 4, or 8 ONLY */
	53	#define CONFIG_CCLK_DIV 1
	54	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
	55	/* Values can range from 1-15 */
	56	#define CONFIG_SCLK_DIV 5
	57	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	58	/* Values can range from 2-65535 */
	59	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	60	#define CONFIG_SPI_BAUD 2
	61	#define CONFIG_SPI_BAUD_INITBLOCK 4
	62
	63	/*
	64	* Network settings
	65	*/
	66	#if (CONFIG_DRIVER_SMC91111)
	67	#define CONFIG_IPADDR 192.168.0.15
	68	#define CONFIG_NETMASK 255.255.255.0
	69	#define CONFIG_GATEWAYIP 192.168.0.1
	70	#define CONFIG_SERVERIP 192.168.0.2
	71	#define CONFIG_HOSTNAME ezkit561
	72	#define CONFIG_ROOTPATH /arm-cross-build/BF561/uClinux-dist/romfs
	73	#endif /* CONFIG_DRIVER_SMC91111 */
	74
	75	/*
	76	* Flash settings
	77	*/
	78
	79	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	80	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	81	#define CFG_FLASH_CFI_AMD_RESET
	82	#define CFG_ENV_IS_IN_FLASH 1
	83	#define CFG_FLASH_BASE 0x20000000
	84	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	85	#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
	86	#define CFG_ENV_ADDR 0x20020000
	87	#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
	88	/* JFFS Partition offset set */
	89	#define CFG_JFFS2_FIRST_BANK 0
	90	#define CFG_JFFS2_NUM_BANKS 1
91	/* 512k reserved for u-boot */
92	#define CFG_JFFS2_FIRST_SECTOR 8
93
94	/*
95	* SDRAM settings & memory map
96	*/
97
98	#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
99	#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
100	#define CONFIG_MEM_MT48LC16M16A2TG_75 1
101
102	#define CFG_SDRAM_BASE 0x00000000
103	#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
104
105	#define CFG_MEMTEST_START 0x0 /* memtest works on */
106	#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 10241024) / 1 ... 63 MB in DRAM */
107
108	#define CONFIG_LOADADDR 0x01000000 /* default load address */
109	#define CFG_LOAD_ADDR CONFIG_LOADADDR
110	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
111	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
112
113	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
114	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
115
116	#define CFG_GBL_DATA_SIZE 0x4000
117	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
118	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
119	#define CONFIG_STACKSIZE (1281024) / regular stack */
120
121	#if ( CONFIG_CLKIN_HALF == 0 )
122	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
123	#else
124	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
125	#endif
126
127	#if (CONFIG_PLL_BYPASS == 0)
128	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
129	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
130	#else
131	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
132	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
133	#endif
134
135	/*
136	* Command settings
137	*/
138
139	#define CFG_AUTOLOAD "no" /* rarpb, bootp, dhcp commands will */
140	/* only perform a configuration */
141	/* lookup from the BOOTP/DHCP server */
142	/* but not try to load any image */
143	/* using TFTP */
144	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, */
145	/* currently its disabled */
146	#define CONFIG_BOOTCOMMAND "run ramboot"
147	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
148
149	#if (CONFIG_DRIVER_SMC91111)
65458987	150	#define CONFIG_EXTRA_ENV_SETTINGS \
53677ef1	151	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
65458987	152	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
53677ef1	153	"$(rootpath) console=ttyBF0,57600\0" \
65458987 AL	154	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
65458987 AL	155	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
53677ef1	156	"ramboot=tftpboot $(loadaddr) linux; " \
65458987	157	"run ramargs; run addip; bootelf\0" \
53677ef1	158	"nfsboot=tftpboot $(loadaddr) linux; " \
65458987	159	"run nfsargs; run addip; bootelf\0" \
53677ef1	160	"update=tftpboot $(loadaddr) u-boot.bin; " \
65458987 AL	161	"protect off 0x20000000 0x2003FFFF; " \
65458987 AL	162	"erase 0x20000000 0x2003FFFF; " \
53677ef1	163	"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
65458987 AL	164	""
65458987 AL	165	#else
65458987	166	#define CONFIG_EXTRA_ENV_SETTINGS \
53677ef1	167	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
65458987 AL	168	"flashboot=bootm 0x20100000\0" \
	169	""
	170	#endif
	171
079a136c JL	172	/*
	173	* BOOTP options
	174	*/
	175	#define CONFIG_BOOTP_BOOTFILESIZE
	176	#define CONFIG_BOOTP_BOOTPATH
	177	#define CONFIG_BOOTP_GATEWAY
	178	#define CONFIG_BOOTP_HOSTNAME
	179
ba2351f9 JL	180	/*
	181	* Command line configuration.
	182	*/
	183	#include <config_cmd_default.h>
	184
	185	#define CONFIG_CMD_ELF
	186	#define CONFIG_CMD_CACHE
	187	#define CONFIG_CMD_JFFS2
	188
	189	#if defined(CONFIG_DRIVER_SMC91111)
	190	#define CONFIG_CMD_PING
	191	#define CONFIG_CMD_DHCP
	192	#endif
	193
65458987 AL	194	/*
	195	* Console settings
	196	*/
	197	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	198
f7ce12cb	199	#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
65458987	200
ba2351f9	201	#if defined(CONFIG_CMD_KGDB)
65458987 AL	202	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	203	#else
	204	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	205	#endif
	206	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	207	#define CFG_MAXARGS 16 /* max number of command args */
	208	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	209
	210	#define CONFIG_LOADS_ECHO 1
	211
	212	/*
	213	* Miscellaneous configurable options
	214	*/
	215	#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
	216	#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
	217
	218	/*
	219	* FLASH organization and environment definitions
	220	*/
9171fc81 MF	221	#define CONFIG_EBIU_SDRRC_VAL 0x306
	222	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	223	#define CONFIG_EBIU_SDBCTL_VAL 0x15
65458987	224
9171fc81 MF	225	#define CONFIG_EBIU_AMGCTL_VAL 0x3F
	226	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	227	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
65458987	228
9171fc81	229	#include <asm/blackfin-config-post.h>
65458987 AL	230
65458987 AL	231	#endif /* __CONFIG_EZKIT561_H__ */