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1/*
2 * U-boot - Configuration file for BF561 EZKIT board
3 */
4
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5#ifndef __CONFIG_BF561_EZKIT_H__
6#define __CONFIG_BF561_EZKIT_H__
65458987 7
f348ab85 8#include <asm/config-pre.h>
f7ce12cb 9
65458987 10
65458987 11/*
cf6f469e 12 * Processor Settings
65458987 13 */
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14#define CONFIG_BFIN_CPU bf561-0.3
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
65458987 16
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17
18/*
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19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
65458987 22 */
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23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 30000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 6
65458987 40
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41
42/*
cf6f469e 43 * Memory Settings
65458987 44 */
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45#define CONFIG_MEM_ADD_WDTH 9
46#define CONFIG_MEM_SIZE 64
65458987 47
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48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
65458987 50
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51#define CONFIG_EBIU_AMGCTL_VAL 0x3F
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
65458987 54
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55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
65458987 57
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58
59/*
cf6f469e 60 * Network Settings
65458987 61 */
cf6f469e 62#define ADI_CMDS_NETWORK 1
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63#define CONFIG_NET_MULTI
64#define CONFIG_SMC91111 1
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65#define CONFIG_SMC91111_BASE 0x2C010300
66#define CONFIG_SMC_USE_32_BIT 1
67#define CONFIG_HOSTNAME bf561-ezkit
68/* Uncomment next line to use fixed MAC address */
69/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
65458987 70
079a136c 71
ba2351f9 72/*
cf6f469e 73 * Flash Settings
ba2351f9 74 */
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75#define CONFIG_SYS_FLASH_CFI
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_CFI_AMD_RESET
78#define CONFIG_SYS_FLASH_BASE 0x20000000
79#define CONFIG_SYS_MAX_FLASH_BANKS 1
80#define CONFIG_SYS_MAX_FLASH_SECT 135
81/* The BF561-EZKIT uses a top boot flash */
82#define CONFIG_ENV_IS_IN_FLASH 1
83#define CONFIG_ENV_ADDR 0x20004000
84#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
85#define CONFIG_ENV_SIZE 0x2000
86#define CONFIG_ENV_SECT_SIZE 0x10000
87#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
88#define ENV_IS_EMBEDDED
89#else
76d82187 90#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
ba2351f9 91#endif
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92#ifdef ENV_IS_EMBEDDED
93/* WARNING - the following is hand-optimized to fit within
94 * the sector before the environment sector. If it throws
95 * an error during compilation remove an object here to get
96 * it linked after the configuration sector.
97 */
98# define LDS_BOARD_TEXT \
99 cpu/blackfin/traps.o (.text .text.*); \
100 cpu/blackfin/interrupt.o (.text .text.*); \
101 cpu/blackfin/serial.o (.text .text.*); \
102 common/dlmalloc.o (.text .text.*); \
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103 lib/crc32.o (.text .text.*); \
104 lib/zlib.o (.text .text.*); \
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105 board/bf561-ezkit/bf561-ezkit.o (.text .text.*); \
106 . = DEFINED(env_offset) ? env_offset : .; \
107 common/env_embedded.o (.text .text.*);
108#endif
ba2351f9 109
cf6f469e 110
65458987 111/*
cf6f469e 112 * I2C Settings
65458987 113 */
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114#define CONFIG_SOFT_I2C
115#ifdef CONFIG_SOFT_I2C
116#define PF_SCL PF0
117#define PF_SDA PF1
118#define I2C_INIT \
119 do { \
120 *pFIO0_DIR |= PF_SCL; \
121 SSYNC(); \
122 } while (0)
123#define I2C_ACTIVE \
124 do { \
125 *pFIO0_DIR |= PF_SDA; \
126 *pFIO0_INEN &= ~PF_SDA; \
127 SSYNC(); \
128 } while (0)
129#define I2C_TRISTATE \
130 do { \
131 *pFIO0_DIR &= ~PF_SDA; \
132 *pFIO0_INEN |= PF_SDA; \
133 SSYNC(); \
134 } while (0)
135#define I2C_READ ((*pFIO0_FLAG_D & PF_SDA) != 0)
136#define I2C_SDA(bit) \
137 do { \
138 if (bit) \
139 *pFIO0_FLAG_S = PF_SDA; \
140 else \
141 *pFIO0_FLAG_C = PF_SDA; \
142 SSYNC(); \
143 } while (0)
144#define I2C_SCL(bit) \
145 do { \
146 if (bit) \
147 *pFIO0_FLAG_S = PF_SCL; \
148 else \
149 *pFIO0_FLAG_C = PF_SCL; \
150 SSYNC(); \
151 } while (0)
152#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
153
154#define CONFIG_SYS_I2C_SPEED 50000
155#define CONFIG_SYS_I2C_SLAVE 0
65458987 156#endif
65458987 157
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158
159/*
cf6f469e 160 * Misc Settings
65458987 161 */
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162#define CONFIG_UART_CONSOLE 0
163
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164
165/*
cf6f469e 166 * Pull in common ADI header for remaining command/environment setup
65458987 167 */
cf6f469e 168#include <configs/bfin_adi_common.h>
65458987 169
f348ab85 170#endif