[people/ms/u-boot.git] / include / configs / bf609-ezkit.h

/*
 * U-boot - Configuration file for BF609 EZ-Kit board
 */

#ifndef __CONFIG_BF609_EZKIT_H__
#define __CONFIG_BF609_EZKIT_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf609-0.0
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA


/* For ez-board version 1.0, else undef this */
#define CONFIG_BFIN_BOARD_VERSION_1_0

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
 *	SCLK0 = SCLK / SCLK0_DIV
 *	SCLK1 = SCLK / SCLK1_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			(25000000)
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		(0)

/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-127 (where 0 means 128)			*/
#define CONFIG_VCO_MULT			(20)

/* CCLK_DIV controls the core clock divider				*/
/* Values can range from 0-31 (where 0 means 32)			*/
#define CONFIG_CCLK_DIV			(1)
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 0-31 (where 0 means 32)			*/
#define CONFIG_SCLK_DIV		(4)
/* Values can range from 0-7 (where 0 means 8)				*/
#define CONFIG_SCLK0_DIV		(1)
#define CONFIG_SCLK1_DIV		(1)
/* DCLK_DIV controls the DDR clock divider				*/
/* Values can range from 0-31 (where 0 means 32)			*/
#define CONFIG_DCLK_DIV			(2)
/* OCLK_DIV controls the output clock divider				*/
/* Values can range from 0-127 (where 0 means 128)			*/
#define CONFIG_OCLK_DIV			(16)

/*
 * Memory Settings
 */
#define CONFIG_MEM_SIZE		128

#define CONFIG_SMC_GCTL_VAL	0x00000010
#define CONFIG_SMC_B0CTL_VAL	0x01007011
#define CONFIG_SMC_B0TIM_VAL	0x08170977
#define CONFIG_SMC_B0ETIM_VAL	0x00092231

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)

#define CONFIG_HW_WATCHDOG
/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK
#define CONFIG_NETCONSOLE
#define CONFIG_HOSTNAME		"bf609-ezkit"
#define CONFIG_PHY_ADDR		1
#define CONFIG_DW_PORTS		1
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_PHYLIB

/* i2c Settings */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * Flash Settings
 */
#undef CONFIG_CMD_JFFS2
#define CONFIG_SYS_FLASH_CFI_WIDTH     2
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE          0xb0000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS     1
#define CONFIG_SYS_MAX_FLASH_SECT      131
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI6XX
#define CONFIG_ENV_SPI_MAX_HZ	25000000
#define CONFIG_SF_DEFAULT_SPEED	25000000
#define CONFIG_SPI_FLASH_ALL

/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET       0x10000
#define CONFIG_ENV_SIZE         0x2000
#define CONFIG_ENV_SECT_SIZE    0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET       0x60000
#define CONFIG_ENV_SIZE         0x20000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET       0x8000
#define CONFIG_ENV_SIZE         0x8000
#define CONFIG_ENV_SECT_SIZE    0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif

#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"

/*
 * SDH Settings
 */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH

/*
 * Misc Settings
 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_UART_CONSOLE	0

#define CONFIG_CMD_SOFTSWITCH

#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
#define CONFIG_BFIN_SOFT_SWITCH

#define CONFIG_ADI_GPIO2

#if 0
#define CONFIG_UART_MEM 1024
#undef CONFIG_UART_CONSOLE
#undef CONFIG_JTAG_CONSOLE
#undef CONFIG_UART_CONSOLE_IS_JTAG
#endif

#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))

/*
 * Run core 1 from L1 SRAM start address when init uboot on core 0
 */
/* #define CONFIG_CORE1_RUN	1 */

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>
#endif
Commit	Line	Data
320ec9df SZ	1	/*
	2	* U-boot - Configuration file for BF609 EZ-Kit board
	3	*/
	4
	5	#ifndef __CONFIG_BF609_EZKIT_H__
	6	#define __CONFIG_BF609_EZKIT_H__
	7
	8	#include <asm/config-pre.h>
	9
	10	/*
	11	* Processor Settings
	12	*/
	13	#define CONFIG_BFIN_CPU bf609-0.0
	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
	15
	16
	17	/* For ez-board version 1.0, else undef this */
	18	#define CONFIG_BFIN_BOARD_VERSION_1_0
	19
	20	/*
	21	* Clock Settings
	22	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	23	* SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
	24	* SCLK0 = SCLK / SCLK0_DIV
	25	* SCLK1 = SCLK / SCLK1_DIV
	26	*/
	27	/* CONFIG_CLKIN_HZ is any value in Hz */
	28	#define CONFIG_CLKIN_HZ (25000000)
	29	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	30	/* 1 = CLKIN / 2 */
	31	#define CONFIG_CLKIN_HALF (0)
	32
	33	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	34	/* Values can range from 0-127 (where 0 means 128) */
	35	#define CONFIG_VCO_MULT (20)
	36
	37	/* CCLK_DIV controls the core clock divider */
	38	/* Values can range from 0-31 (where 0 means 32) */
	39	#define CONFIG_CCLK_DIV (1)
	40	/* SCLK_DIV controls the system clock divider */
	41	/* Values can range from 0-31 (where 0 means 32) */
	42	#define CONFIG_SCLK_DIV (4)
	43	/* Values can range from 0-7 (where 0 means 8) */
	44	#define CONFIG_SCLK0_DIV (1)
	45	#define CONFIG_SCLK1_DIV (1)
	46	/* DCLK_DIV controls the DDR clock divider */
	47	/* Values can range from 0-31 (where 0 means 32) */
	48	#define CONFIG_DCLK_DIV (2)
	49	/* OCLK_DIV controls the output clock divider */
	50	/* Values can range from 0-127 (where 0 means 128) */
	51	#define CONFIG_OCLK_DIV (16)
	52
	53	/*
	54	* Memory Settings
	55	*/
	56	#define CONFIG_MEM_SIZE 128
	57
	58	#define CONFIG_SMC_GCTL_VAL 0x00000010
	59	#define CONFIG_SMC_B0CTL_VAL 0x01007011
	60	#define CONFIG_SMC_B0TIM_VAL 0x08170977
	61	#define CONFIG_SMC_B0ETIM_VAL 0x00092231
	62
	63	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	64	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
65
49c2da53	66	#define CONFIG_HW_WATCHDOG
320ec9df SZ	67	/*
	68	* Network Settings
	69	*/
	70	#define ADI_CMDS_NETWORK
	71	#define CONFIG_NETCONSOLE
320ec9df	72	#define CONFIG_HOSTNAME "bf609-ezkit"
92a190aa	73	#define CONFIG_PHY_ADDR 1
320ec9df	74	#define CONFIG_DW_PORTS 1
320ec9df	75	#define CONFIG_DW_ALTDESCRIPTOR
320ec9df SZ	76	#define CONFIG_CMD_MII
320ec9df SZ	77	#define CONFIG_MII
92a190aa	78	#define CONFIG_PHYLIB
320ec9df SZ	79
320ec9df SZ	80	/* i2c Settings */
c469703b	81	#define CONFIG_SYS_I2C
fea9b69a	82	#define CONFIG_SYS_I2C_ADI
320ec9df SZ	83
	84	/*
	85	* Flash Settings
	86	*/
320ec9df SZ	87	#undef CONFIG_CMD_JFFS2
	88	#define CONFIG_SYS_FLASH_CFI_WIDTH 2
	89	#define CONFIG_FLASH_CFI_DRIVER
	90	#define CONFIG_SYS_FLASH_BASE 0xb0000000
	91	#define CONFIG_SYS_FLASH_CFI
	92	#define CONFIG_SYS_FLASH_PROTECTION
	93	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	94	#define CONFIG_SYS_MAX_FLASH_SECT 131
	95	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	96
	97	/*
	98	* SPI Settings
	99	*/
	100	#define CONFIG_BFIN_SPI6XX
	101	#define CONFIG_ENV_SPI_MAX_HZ 25000000
	102	#define CONFIG_SF_DEFAULT_SPEED 25000000
320ec9df SZ	103	#define CONFIG_SPI_FLASH_ALL
	104
	105	/*
	106	* Env Storage Settings
	107	*/
	108	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	109	#define CONFIG_ENV_IS_IN_SPI_FLASH
	110	#define CONFIG_ENV_OFFSET 0x10000
	111	#define CONFIG_ENV_SIZE 0x2000
	112	#define CONFIG_ENV_SECT_SIZE 0x10000
	113	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
	114	#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
	115	#define CONFIG_ENV_IS_IN_NAND
	116	#define CONFIG_ENV_OFFSET 0x60000
	117	#define CONFIG_ENV_SIZE 0x20000
	118	#else
	119	#define CONFIG_ENV_IS_IN_FLASH
	120	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	121	#define CONFIG_ENV_OFFSET 0x8000
	122	#define CONFIG_ENV_SIZE 0x8000
	123	#define CONFIG_ENV_SECT_SIZE 0x8000
	124	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
	125	#endif
	126
	127	#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
	128
	129	/*
	130	* SDH Settings
	131	*/
	132	#define CONFIG_GENERIC_MMC
	133	#define CONFIG_MMC
	134	#define CONFIG_BFIN_SDH
	135
	136	/*
	137	* Misc Settings
	138	*/
	139	#define CONFIG_BOARD_EARLY_INIT_F
	140	#define CONFIG_UART_CONSOLE 0
	141
7d861d95	142	#define CONFIG_CMD_SOFTSWITCH
320ec9df SZ	143
	144	#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 2010241024 + 4)
	145	#define CONFIG_BFIN_SOFT_SWITCH
	146
da34aae5 SZ	147	#define CONFIG_ADI_GPIO2
da34aae5 SZ	148
320ec9df SZ	149	#if 0
	150	#define CONFIG_UART_MEM 1024
	151	#undef CONFIG_UART_CONSOLE
	152	#undef CONFIG_JTAG_CONSOLE
	153	#undef CONFIG_UART_CONSOLE_IS_JTAG
	154	#endif
	155
955020c6 SZ	156	#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
955020c6 SZ	157
f4d80384 SZ	158	/*
	159	* Run core 1 from L1 SRAM start address when init uboot on core 0
	160	*/
	161	/* #define CONFIG_CORE1_RUN 1 */
	162
320ec9df SZ	163	/*
	164	* Pull in common ADI header for remaining command/environment setup
	165	*/
	166	#include <configs/bfin_adi_common.h>
	167	#endif