[thirdparty/u-boot.git] / include / configs / brppt1.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * brtpp1.h
 *
 * specific parts for B&R T-Series Motherboard
 *
 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
 */

#ifndef __CONFIG_BRPPT1_H__
#define __CONFIG_BRPPT1_H__

#include <configs/bur_cfg_common.h>
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
/* memory */
#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN		SZ_32M

/* Clock Defines */
#define V_OSCK				26000000  /* Clock output from T2 */
#define V_SCLK				(V_OSCK)

#define CONFIG_POWER_TPS65217

/* Support both device trees and ATAGs. */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*#define CONFIG_MACH_TYPE		3589*/
#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/

/*
 * When we have NAND flash we expect to be making use of mtdparts,
 * both for ease of use in U-Boot and for passing information on to
 * the Linux kernel.
 */

#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000

/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */

/* NAND */
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
#endif /* CONFIG_NAND */
#endif /* CONFIG_SPL_OS_BOOT */

#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#endif /* CONFIG_NAND */

#ifdef CONFIG_NAND
#define NANDTGTS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
	"root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
	"run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
"b_tgts_std=usb0 nand net\0" \
"b_tgts_rcy=net usb0 nand\0" \
"b_tgts_pme=usb0 nand net\0"
#else
#define NANDTGTS ""
#endif /* CONFIG_NAND */

#define MMCSPI_TGTS \
"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
	"b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
"b_t30lgcy#0=" \
	"load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
	"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
	"load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
	"run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
	"b_mode=${b_mode}\0" \
"b_t30lgcy#1=" \
	"load ${loaddev}:1 ${loadaddr} zImage && " \
	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
	"load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
	"run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
"b_tgts_rcy=t30lgcy#1 usb0 net\0" \
"b_tgts_pme=net usb0 mmc0 mmc1\0" \
"loaddev=mmc 1\0"

#ifdef CONFIG_ENV_IS_IN_MMC
#define MMCTGTS \
MMCSPI_TGTS \
"cfgscr=mw ${dtbaddr} 0;" \
" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define MMCTGTS ""
#endif /* CONFIG_MMC */

#ifdef CONFIG_SPI
#define SPITGTS \
MMCSPI_TGTS \
"cfgscr=mw ${dtbaddr} 0;" \
" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
#else
#define SPITGTS ""
#endif /* CONFIG_SPI */

#define LOAD_OFFSET(x)			0x8##x

#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
BUR_COMMON_ENV \
"verify=no\0" \
"autoload=0\0" \
"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
"console=ttyO0,115200n8\0" \
"optargs=consoleblank=0 quiet panic=2\0" \
"b_break=0\0" \
"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
MMCTGTS \
SPITGTS \
NANDTGTS \
"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
" else setenv b_tgts ${b_tgts_std}; fi\0" \
"b_default=run b_deftgts; for target in ${b_tgts};"\
" do echo \"### booting ${target} ###\"; run b_${target};" \
" if test ${b_break} = 1; then; exit; fi; done\0"
#endif /* !CONFIG_SPL_BUILD*/

#ifdef CONFIG_NAND
/*
 * GPMC  block.  We support 1 device and the physical address to
 * access CS0 at is 0x8000000.
 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x8000000
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
					10, 11, 12, 13, 14, 15, 16, 17, \
					18, 19, 20, 21, 22, 23, 24, 25, \
					26, 27, 28, 29, 30, 31, 32, 33, \
					34, 35, 36, 37, 38, 39, 40, 41, \
					42, 43, 44, 45, 46, 47, 48, 49, \
					50, 51, 52, 53, 54, 55, 56, 57, }

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_NAND_OMAP_GPMC_WSCFG	1
#endif /* CONFIG_NAND */

#if defined(CONFIG_SPI)
/* SPI Flash */
/* Environment */
#elif defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV		1
#define CONFIG_SYS_MMC_ENV_PART		2

#elif defined(CONFIG_ENV_IS_IN_NAND)
/* No NAND env support in SPL */
#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
#else
#error "no storage for Environment defined!"
#endif

#endif	/* ! __CONFIG_BRPPT1_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
893c04e1	2	/*
2290fe06	3	* brtpp1.h
893c04e1 HP	4	*
	5	* specific parts for B&R T-Series Motherboard
	6	*
4c302b9a	7	* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
893c04e1	8	* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
893c04e1 HP	9	*/
893c04e1 HP	10
2290fe06 HS	11	#ifndef __CONFIG_BRPPT1_H__
2290fe06 HS	12	#define __CONFIG_BRPPT1_H__
893c04e1	13
3b804d94	14	#include <configs/bur_cfg_common.h>
893c04e1 HP	15	#include <configs/bur_am335x_common.h>
893c04e1 HP	16	/* ------------------------------------------------------------------------- */
3b804d94 HS	17	/* memory */
3b804d94 HS	18	#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024)
73e9db22	19	#define CONFIG_SYS_BOOTM_LEN SZ_32M
3b804d94	20
893c04e1 HP	21	/* Clock Defines */
	22	#define V_OSCK 26000000 /* Clock output from T2 */
	23	#define V_SCLK (V_OSCK)
	24
	25	#define CONFIG_POWER_TPS65217
	26
	27	/* Support both device trees and ATAGs. */
893c04e1 HP	28	#define CONFIG_CMDLINE_TAG
	29	#define CONFIG_SETUP_MEMORY_TAGS
	30	#define CONFIG_INITRD_TAG
893c04e1 HP	31	/#define CONFIG_MACH_TYPE 3589/
	32	#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/
	33
893c04e1	34	/*
fbc7c7de	35	* When we have NAND flash we expect to be making use of mtdparts,
893c04e1 HP	36	* both for ease of use in U-Boot and for passing information on to
	37	* the Linux kernel.
	38	*/
9c5b0097 AF	39
	40	#ifdef CONFIG_SPL_OS_BOOT
	41	#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
	42
	43	/* RAW SD card / eMMC */
	44	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
	45	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
	46	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
	47
	48	/* NAND */
	49	#ifdef CONFIG_NAND
	50	#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000
	51	#endif /* CONFIG_NAND */
	52	#endif /* CONFIG_SPL_OS_BOOT */
893c04e1	53
893c04e1	54	#ifdef CONFIG_NAND
893c04e1 HP	55	#define CONFIG_SPL_NAND_BASE
	56	#define CONFIG_SPL_NAND_DRIVERS
	57	#define CONFIG_SPL_NAND_ECC
	58	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	59	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	60	#endif /* CONFIG_NAND */
	61
893c04e1	62	#ifdef CONFIG_NAND
73e9db22 HS	63	#define NANDTGTS \
	64	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	65	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
0ea4fc4d HS	66	"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
0ea4fc4d HS	67	" fdt addr ${dtbaddr} \|\| cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
73e9db22 HS	68	"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
	69	"root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
	70	"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
	71	"run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
	72	"b_tgts_std=usb0 nand net\0" \
	73	"b_tgts_rcy=net usb0 nand\0" \
	74	"b_tgts_pme=usb0 nand net\0"
893c04e1	75	#else
73e9db22	76	#define NANDTGTS ""
893c04e1 HP	77	#endif /* CONFIG_NAND */
893c04e1 HP	78
73e9db22 HS	79	#define MMCSPI_TGTS \
	80	"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
	81	"b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
	82	"b_t30lgcy#0=" \
	83	"load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
	84	"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
	85	"load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb \|\| " \
	86	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
	87	"run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
	88	"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
	89	"b_mode=${b_mode}\0" \
	90	"b_t30lgcy#1=" \
	91	"load ${loaddev}:1 ${loadaddr} zImage && " \
	92	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
	93	"load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
	94	"run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
	95	"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
	96	"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
	97	"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
	98	"b_tgts_rcy=t30lgcy#1 usb0 net\0" \
	99	"b_tgts_pme=net usb0 mmc0 mmc1\0" \
	100	"loaddev=mmc 1\0"
	101
fbc7c7de	102	#ifdef CONFIG_ENV_IS_IN_MMC
73e9db22 HS	103	#define MMCTGTS \
73e9db22 HS	104	MMCSPI_TGTS \
0ea4fc4d HS	105	"cfgscr=mw ${dtbaddr} 0;" \
	106	" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
	107	" fdt addr ${dtbaddr} \|\| cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
893c04e1	108	#else
73e9db22	109	#define MMCTGTS ""
893c04e1 HP	110	#endif /* CONFIG_MMC */
893c04e1 HP	111
73e9db22 HS	112	#ifdef CONFIG_SPI
	113	#define SPITGTS \
	114	MMCSPI_TGTS \
0ea4fc4d HS	115	"cfgscr=mw ${dtbaddr} 0;" \
	116	" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
	117	" fdt addr ${dtbaddr} \|\| cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
73e9db22 HS	118	#else
	119	#define SPITGTS ""
	120	#endif /* CONFIG_SPI */
	121
	122	#define LOAD_OFFSET(x) 0x8##x
	123
893c04e1 HP	124	#ifndef CONFIG_SPL_BUILD
893c04e1 HP	125	#define CONFIG_EXTRA_ENV_SETTINGS \
7ae47f6b	126	BUR_COMMON_ENV \
662a4765	127	"verify=no\0" \
7ae47f6b	128	"autoload=0\0" \
73e9db22 HS	129	"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
	130	"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
	131	"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
	132	"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
	133	"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
662a4765	134	"console=ttyO0,115200n8\0" \
14ec12fa	135	"optargs=consoleblank=0 quiet panic=2\0" \
73e9db22 HS	136	"b_break=0\0" \
	137	"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
	138	"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
	139	MMCTGTS \
	140	SPITGTS \
	141	NANDTGTS \
	142	"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
	143	" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
	144	" else setenv b_tgts ${b_tgts_std}; fi\0" \
	145	"b_default=run b_deftgts; for target in ${b_tgts};"\
	146	" do echo \"### booting ${target} ###\"; run b_${target};" \
	147	" if test ${b_break} = 1; then; exit; fi; done\0"
893c04e1 HP	148	#endif /* !CONFIG_SPL_BUILD*/
893c04e1 HP	149
893c04e1 HP	150	#ifdef CONFIG_NAND
	151	/*
	152	* GPMC block. We support 1 device and the physical address to
	153	* access CS0 at is 0x8000000.
	154	*/
	155	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	156	#define CONFIG_SYS_NAND_BASE 0x8000000
893c04e1	157	/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
893c04e1	158	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
893c04e1 HP	159	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	160	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	161	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	162	#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
	163	CONFIG_SYS_NAND_PAGE_SIZE)
	164	#define CONFIG_SYS_NAND_OOBSIZE 64
	165	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	166	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
	167	10, 11, 12, 13, 14, 15, 16, 17, \
	168	18, 19, 20, 21, 22, 23, 24, 25, \
	169	26, 27, 28, 29, 30, 31, 32, 33, \
	170	34, 35, 36, 37, 38, 39, 40, 41, \
	171	42, 43, 44, 45, 46, 47, 48, 49, \
	172	50, 51, 52, 53, 54, 55, 56, 57, }
	173
	174	#define CONFIG_SYS_NAND_ECCSIZE 512
	175	#define CONFIG_SYS_NAND_ECCBYTES 14
	176
	177	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
893c04e1	178
d79c138c	179	#define CONFIG_NAND_OMAP_GPMC_WSCFG 1
893c04e1 HP	180	#endif /* CONFIG_NAND */
893c04e1 HP	181
fbc7c7de HS	182	#if defined(CONFIG_SPI)
fbc7c7de HS	183	/* SPI Flash */
fbc7c7de	184	/* Environment */
fbc7c7de	185	#elif defined(CONFIG_ENV_IS_IN_MMC)
29e00313	186	#define CONFIG_SYS_MMC_ENV_DEV 1
893c04e1	187	#define CONFIG_SYS_MMC_ENV_PART 2
893c04e1	188
fbc7c7de	189	#elif defined(CONFIG_ENV_IS_IN_NAND)
e017fd61	190	/* No NAND env support in SPL */
893c04e1 HP	191	#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE
	192	#else
	193	#error "no storage for Environment defined!"
	194	#endif
893c04e1	195
2290fe06	196	#endif /* ! __CONFIG_BRPPT1_H__ */