[people/ms/u-boot.git] / include / configs / bur_am335x_common.h

/*
 * bur_am335x_common.h
 *
 * common parts used by B&R AM335x based boards
 *
 * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
 *
 * SPDX-License-Identifier:        GPL-2.0+
 */

#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */

/* Timer information */
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC	/* enable 32kHz OSC at bootime */
#define CONFIG_POWER_TPS65217

#define CONFIG_SYS_NO_FLASH		/* have no NOR-flash */

#include <asm/arch/omap.h>

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000
#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
#define CONFIG_BAUDRATE			115200

/* Network defines */
#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
#define CONFIG_MII			/* Required in net/eth.c */
#define CONFIG_PHYLIB
#define CONFIG_PHY_NATSEMI

/*
 * SPL related defines.  The Public RAM memory map the ROM defines the
 * area between 0x402F0400 and 0x4030B800 as a download area and
 * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
 * supports X-MODEM loading via UART, and we leverage this and then use
 * Y-MODEM to load u-boot.img, when booted over UART.  We must also include
 * the scratch space that U-Boot uses in SRAM.
 */
#define CONFIG_SPL_TEXT_BASE		0x402F0400
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

/*
 * Since SPL did pll and ddr initialization for us,
 * we don't need to do it twice.
 */
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif /* !CONFIG_SPL_BUILD, ... */
/*
 * Our DDR memory always starts at 0x80000000 and U-Boot shall have
 * relocated itself to higher in memory by the time this value is used.
 */
#define CONFIG_SYS_LOAD_ADDR		0x80000000
/*
 * ----------------------------------------------------------------------------
 * DDR information.  We say (for simplicity) that we have 1 bank,
 * always, even when we have more.  We always start at 0x80000000,
 * and we place the initial stack pointer in our SRAM.
 */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
					GENERATED_GBL_DATA_SIZE)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP24XX
/* GPIO */
#define CONFIG_OMAP_GPIO

/*
 * Our platforms make use of SPL to initalize the hardware (primarily
 * memory) enough for full U-Boot to be loaded.  We also support Falcon
 * Mode so that the Linux kernel can be booted directly from SPL
 * instead, if desired.  We make use of the general SPL framework found
 * under common/spl/.  Given our generally common memory map, we set a
 * number of related defaults and sizes here.
 */
#define CONFIG_SPL_FRAMEWORK
/*
 * Place the image at the start of the ROM defined image space.
 * We limit our size to the ROM-defined downloaded image area, and use the
 * rest of the space for stack.  We load U-Boot itself into memory at
 * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
 * have our BSS be placed 1MiB after this, to allow for the default
 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
 * We have the SPL malloc pool at the end of the BSS area.
 *
 * ----------------------------------------------------------------------------
 */
#undef  CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x80800000
#define CONFIG_SPL_BSS_START_ADDR	0x80A00000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN

/* General parts of the framework, required. */
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"

#endif	/* ! __BUR_AM335X_COMMON_H__ */
Commit	Line	Data
893c04e1 HP	1	/*
	2	* bur_am335x_common.h
	3	*
	4	* common parts used by B&R AM335x based boards
	5	*
3b804d94	6	* Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
893c04e1 HP	7	* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#ifndef __BUR_AM335X_COMMON_H__
	13	#define __BUR_AM335X_COMMON_H__
	14	/* ------------------------------------------------------------------------- */
	15	#define CONFIG_AM33XX
	16	#define CONFIG_OMAP
	17	#define CONFIG_OMAP_COMMON
893c04e1 HP	18	#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
	19
	20	/* Timer information */
	21	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	22	#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
96de041e	23	#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */
893c04e1 HP	24	#define CONFIG_POWER_TPS65217
	25
	26	#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
	27
	28	#include <asm/arch/omap.h>
	29
	30	/* NS16550 Configuration */
893c04e1 HP	31	#define CONFIG_SYS_NS16550_SERIAL
	32	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	33	#define CONFIG_SYS_NS16550_CLK 48000000
	34	#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
	35	#define CONFIG_BAUDRATE 115200
	36
	37	/* Network defines */
893c04e1 HP	38	#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
893c04e1 HP	39	#define CONFIG_MII /* Required in net/eth.c */
893c04e1	40	#define CONFIG_PHYLIB
893c04e1	41	#define CONFIG_PHY_NATSEMI
3b804d94	42
893c04e1 HP	43	/*
	44	* SPL related defines. The Public RAM memory map the ROM defines the
	45	* area between 0x402F0400 and 0x4030B800 as a download area and
	46	* 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
	47	* supports X-MODEM loading via UART, and we leverage this and then use
fa2f81b0 TR	48	* Y-MODEM to load u-boot.img, when booted over UART. We must also include
fa2f81b0 TR	49	* the scratch space that U-Boot uses in SRAM.
893c04e1 HP	50	*/
893c04e1 HP	51	#define CONFIG_SPL_TEXT_BASE 0x402F0400
fa2f81b0 TR	52	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	53	CONFIG_SPL_TEXT_BASE)
893c04e1 HP	54
	55	/*
	56	* Since SPL did pll and ddr initialization for us,
	57	* we don't need to do it twice.
	58	*/
	59	#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
	60	#define CONFIG_SKIP_LOWLEVEL_INIT
	61	#endif /* !CONFIG_SPL_BUILD, ... */
	62	/*
	63	* Our DDR memory always starts at 0x80000000 and U-Boot shall have
	64	* relocated itself to higher in memory by the time this value is used.
	65	*/
	66	#define CONFIG_SYS_LOAD_ADDR 0x80000000
	67	/*
	68	* ----------------------------------------------------------------------------
	69	* DDR information. We say (for simplicity) that we have 1 bank,
	70	* always, even when we have more. We always start at 0x80000000,
	71	* and we place the initial stack pointer in our SRAM.
	72	*/
	73	#define CONFIG_NR_DRAM_BANKS 1
	74	#define CONFIG_SYS_SDRAM_BASE 0x80000000
	75	#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
	76	GENERATED_GBL_DATA_SIZE)
	77
	78	/* I2C */
	79	#define CONFIG_SYS_I2C
	80	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	81	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	82	#define CONFIG_SYS_I2C_OMAP24XX
893c04e1 HP	83	/* GPIO */
893c04e1 HP	84	#define CONFIG_OMAP_GPIO
893c04e1 HP	85
	86	/*
	87	* Our platforms make use of SPL to initalize the hardware (primarily
	88	* memory) enough for full U-Boot to be loaded. We also support Falcon
	89	* Mode so that the Linux kernel can be booted directly from SPL
	90	* instead, if desired. We make use of the general SPL framework found
	91	* under common/spl/. Given our generally common memory map, we set a
	92	* number of related defaults and sizes here.
	93	*/
893c04e1 HP	94	#define CONFIG_SPL_FRAMEWORK
	95	/*
	96	* Place the image at the start of the ROM defined image space.
	97	* We limit our size to the ROM-defined downloaded image area, and use the
	98	* rest of the space for stack. We load U-Boot itself into memory at
	99	* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
	100	* have our BSS be placed 1MiB after this, to allow for the default
	101	* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
	102	* We have the SPL malloc pool at the end of the BSS area.
	103	*
	104	* ----------------------------------------------------------------------------
	105	*/
893c04e1 HP	106	#undef CONFIG_SYS_TEXT_BASE
	107	#define CONFIG_SYS_TEXT_BASE 0x80800000
	108	#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
	109	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	110	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	111	CONFIG_SPL_BSS_MAX_SIZE)
	112	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
	113
	114	/* General parts of the framework, required. */
893c04e1 HP	115	#define CONFIG_SPL_BOARD_INIT
	116	#define CONFIG_SPL_YMODEM_SUPPORT
	117	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
	118
	119	#endif /* ! __BUR_AM335X_COMMON_H__ */