[people/ms/u-boot.git] / include / configs / c2mon.h

/*
 * (C) Copyright 2001-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
#define CONFIG_C2MON		1	/* ...on a C2MON module		*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_80MHz		1	/* Running at 5 * 16 = 80 MHz	*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_FEC_ENET		1	/* Use Fast Ethernet Controller	*/

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CONFIG_SYS_PLPRCR							\
		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
#else			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#endif	/* CONFIG_80MHz */

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#else			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#endif	/* CONFIG_80MHz */

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * PCMCIA Power Switch
 *
 * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
 * control the voltages on the PCMCIA slot which is connected
 * to Port C (all outputs) and Port B (Over-Current Input)
 *-----------------------------------------------------------------------
 */
			/* Output pins */
#define TPS2211_VCCD0	0x0002		/* PC.14 */
#define TPS2211_VCCD1	0x0004		/* PC.13 */
#define TPS2211_VPPD0	0x0008		/* PC.12 */
#define TPS2211_VPPD1	0x0010		/* PC.11 */
#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
			  TPS2211_VPPD0 | TPS2211_VPPD1 )

			/* Input pins */
#define TPS2211_OC	0x00000200	/* PB.22: Over-Current		*/
#define TPS2211_INPUTS	( TPS2211_OC )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100


/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768	1	/*
414eec35	2	* (C) Copyright 2001-2005
0f8c9768 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
	37	#define CONFIG_C2MON 1 /* ...on a C2MON module */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
0f8c9768 WD	41	#define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */
	42
	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
	46	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	47	#if 0
	48	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	49	#else
	50	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	51	#endif
	52
	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	54
32bf3d14	55	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
0f8c9768 WD	56
	57	#undef CONFIG_BOOTARGS
	58	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	59	"bootp; " \
	60	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	61	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
0f8c9768 WD	62	"bootm"
	63
	64	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	65	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	66
	67	#undef CONFIG_WATCHDOG /* watchdog disabled */
	68
	69	#undef CONFIG_STATUS_LED /* Status LED disabled */
	70
	71	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	72
2fd90ce5 JL	73	/*
	74	* BOOTP options
	75	*/
	76	#define CONFIG_BOOTP_SUBNETMASK
	77	#define CONFIG_BOOTP_GATEWAY
	78	#define CONFIG_BOOTP_HOSTNAME
	79	#define CONFIG_BOOTP_BOOTPATH
	80	#define CONFIG_BOOTP_BOOTFILESIZE
	81
0f8c9768 WD	82
	83	#define CONFIG_MAC_PARTITION
	84	#define CONFIG_DOS_PARTITION
	85
	86	#define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */
	87
	88	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	89
0f8c9768	90
37e4f24b JL	91	/*
	92	* Command line configuration.
	93	*/
	94	#include <config_cmd_default.h>
	95
	96	#define CONFIG_CMD_DATE
	97	#define CONFIG_CMD_DHCP
	98	#define CONFIG_CMD_IDE
	99	#define CONFIG_CMD_NFS
	100	#define CONFIG_CMD_SNTP
	101
0f8c9768 WD	102
	103	/*
	104	* Miscellaneous configurable options
	105	*/
6d0f6bcf JCPV	106	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	107	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
0f8c9768	108
6d0f6bcf	109	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
0f8c9768	110
37e4f24b	111	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	112	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	113	#else
6d0f6bcf	114	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	115	#endif
6d0f6bcf JCPV	116	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	117	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	118	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	121	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
0f8c9768	122
6d0f6bcf	123	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	124
6d0f6bcf	125	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	126
0f8c9768 WD	127	/*
	128	* Low Level Configuration Settings
	129	* (address mappings, register initial values, etc.)
	130	* You should know what you are doing if you make changes here.
	131	*/
	132	/*-----------------------------------------------------------------------
	133	* Internal Memory Mapped Register
	134	*/
6d0f6bcf	135	#define CONFIG_SYS_IMMR 0xFFF00000
0f8c9768 WD	136
	137	/*-----------------------------------------------------------------------
	138	* Definitions for initial stack pointer and data area (in DPRAM)
	139	*/
6d0f6bcf	140	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	141	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	142	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	143	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	144
	145	/*-----------------------------------------------------------------------
	146	* Start addresses for the final memory configuration
	147	* (Set up by the startup code)
6d0f6bcf	148	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	149	*/
6d0f6bcf JCPV	150	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	151	#define CONFIG_SYS_FLASH_BASE 0x40000000
0f8c9768	152	#if defined(DEBUG)
6d0f6bcf	153	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
0f8c9768	154	#else
6d0f6bcf	155	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
0f8c9768	156	#endif
6d0f6bcf JCPV	157	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	158	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	159
	160	/*
	161	* For booting Linux, the board info and command line data
	162	* have to be in the first 8 MB of memory, since this is
	163	* the maximum mapped by the Linux kernel during initialization.
	164	*/
6d0f6bcf	165	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	166
	167	/*-----------------------------------------------------------------------
	168	* FLASH organization
	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	171	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
0f8c9768	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	175
5a1aceb0	176	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	177	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	178	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
0f8c9768 WD	179
	180	/*-----------------------------------------------------------------------
	181	* Cache Configuration
	182	*/
6d0f6bcf	183	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
37e4f24b	184	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	185	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	186	#endif
	187
	188	/*-----------------------------------------------------------------------
	189	* SYPCR - System Protection Control 11-9
	190	* SYPCR can only be written once after reset!
	191	*-----------------------------------------------------------------------
	192	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	193	*/
	194	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	195	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	196	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768 WD	197	#else
6d0f6bcf	198	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	199	#endif
	200
	201	/*-----------------------------------------------------------------------
	202	* SIUMCR - SIU Module Configuration 11-6
	203	*-----------------------------------------------------------------------
	204	* PCMCIA config., multi-function pin tri-state
	205	*/
	206	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	207	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
0f8c9768	208	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	209	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
0f8c9768 WD	210	#endif /* CONFIG_CAN_DRIVER */
	211
	212	/*-----------------------------------------------------------------------
	213	* TBSCR - Time Base Status and Control 11-26
	214	*-----------------------------------------------------------------------
	215	* Clear Reference Interrupt Status, Timebase freezing enabled
	216	*/
6d0f6bcf	217	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0f8c9768 WD	218
	219	/*-----------------------------------------------------------------------
	220	* RTCSC - Real-Time Clock Status and Control Register 11-27
	221	*-----------------------------------------------------------------------
	222	*/
6d0f6bcf	223	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
0f8c9768 WD	224
	225	/*-----------------------------------------------------------------------
	226	* PISCR - Periodic Interrupt Status and Control 11-31
	227	*-----------------------------------------------------------------------
	228	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	229	*/
6d0f6bcf	230	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	231
	232	/*-----------------------------------------------------------------------
	233	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	234	*-----------------------------------------------------------------------
	235	* Reset PLL lock status sticky bit, timer expired status bit and timer
	236	* interrupt status bit
	237	*
	238	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	239	*/
	240	#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
6d0f6bcf	241	#define CONFIG_SYS_PLPRCR \
0f8c9768 WD	242	( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
0f8c9768 WD	243	#else /* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	244	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
0f8c9768 WD	245	#endif /* CONFIG_80MHz */
	246
	247	/*-----------------------------------------------------------------------
	248	* SCCR - System Clock and reset Control Register 15-27
	249	*-----------------------------------------------------------------------
	250	* Set clock output, timebase and RTC source and divider,
	251	* power management and some other internal clocks
	252	*/
	253	#define SCCR_MASK SCCR_EBDF11
	254	#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
6d0f6bcf	255	#define CONFIG_SYS_SCCR (/* SCCR_TBS \| */ \
0f8c9768 WD	256	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	257	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	258	SCCR_DFALCD00)
	259	#else /* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	260	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
0f8c9768 WD	261	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	262	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	263	SCCR_DFALCD00)
	264	#endif /* CONFIG_80MHz */
	265
	266	/*-----------------------------------------------------------------------
	267	* PCMCIA stuff
	268	*-----------------------------------------------------------------------
	269	*
	270	*/
6d0f6bcf JCPV	271	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	272	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	273	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	274	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	275	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	276	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	277	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	278	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768 WD	279
	280	/*-----------------------------------------------------------------------
	281	* PCMCIA Power Switch
	282	*
	283	* The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
	284	* control the voltages on the PCMCIA slot which is connected
	285	* to Port C (all outputs) and Port B (Over-Current Input)
	286	*-----------------------------------------------------------------------
	287	*/
	288	/* Output pins */
	289	#define TPS2211_VCCD0 0x0002 /* PC.14 */
	290	#define TPS2211_VCCD1 0x0004 /* PC.13 */
	291	#define TPS2211_VPPD0 0x0008 /* PC.12 */
	292	#define TPS2211_VPPD1 0x0010 /* PC.11 */
	293	#define TPS2211_OUTPUTS ( TPS2211_VCCD0 \| TPS2211_VCCD1 \| \
	294	TPS2211_VPPD0 \| TPS2211_VPPD1 )
	295
	296	/* Input pins */
	297	#define TPS2211_OC 0x00000200 /* PB.22: Over-Current */
	298	#define TPS2211_INPUTS ( TPS2211_OC )
	299
	300	/*-----------------------------------------------------------------------
	301	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	302	*-----------------------------------------------------------------------
	303	*/
	304
	305	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	306
	307	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	308	#undef CONFIG_IDE_LED /* LED for ide not supported */
	309	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	312	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
0f8c9768	313
6d0f6bcf	314	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
0f8c9768	315
6d0f6bcf	316	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
0f8c9768 WD	317
0f8c9768 WD	318	/* Offset for data I/O */
6d0f6bcf	319	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0f8c9768 WD	320
0f8c9768 WD	321	/* Offset for normal register accesses */
6d0f6bcf	322	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0f8c9768 WD	323
0f8c9768 WD	324	/* Offset for alternate registers */
6d0f6bcf	325	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
0f8c9768 WD	326
	327
	328	/*-----------------------------------------------------------------------
	329	*
	330	*-----------------------------------------------------------------------
	331	*
	332	*/
6d0f6bcf	333	#define CONFIG_SYS_DER 0
0f8c9768 WD	334
	335	/*
	336	* Init Memory Controller:
	337	*
	338	* BR0/1 and OR0/1 (FLASH)
	339	*/
	340
	341	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	342	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	343
	344	/* used to re-map FLASH both when starting from SRAM or FLASH:
	345	* restrict access enough to keep SRAM working (if any)
	346	* but not too much to meddle with FLASH accesses
	347	*/
6d0f6bcf JCPV	348	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	349	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
0f8c9768 WD	350
0f8c9768 WD	351	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	352	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
0f8c9768 WD	353	OR_SCY_5_CLK \| OR_EHTR)
0f8c9768 WD	354
6d0f6bcf JCPV	355	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	356	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	357	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
0f8c9768	358
6d0f6bcf JCPV	359	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	360	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	361	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_V )
0f8c9768 WD	362
	363	/*
	364	* BR2/3 and OR2/3 (SDRAM)
	365	*
	366	*/
	367	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	368	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	369	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	370
	371	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	372	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
0f8c9768	373
6d0f6bcf JCPV	374	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	375	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
0f8c9768 WD	376
0f8c9768 WD	377	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	378	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	379	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
0f8c9768	380	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	381	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	382	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	383	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	384	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
0f8c9768 WD	385	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	386	#endif /* CONFIG_CAN_DRIVER */
	387
	388	/*
	389	* Memory Periodic Timer Prescaler
	390	*/
	391
	392	/* periodic timer for refresh */
6d0f6bcf	393	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
0f8c9768 WD	394
0f8c9768 WD	395	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	396	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	397	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	398
0f8c9768 WD	399	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	400	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	401	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768 WD	402
	403	/*
	404	* MAMR settings for SDRAM
	405	*/
	406
	407	/* 8 column SDRAM */
6d0f6bcf	408	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
0f8c9768 WD	409	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	410	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	411	/* 9 column SDRAM */
6d0f6bcf	412	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
0f8c9768 WD	413	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	414	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	415
0f8c9768	416	#endif /* __CONFIG_H */