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9a3aae22 | 1 | /* |
30493aac | 2 | * Copyright (C) 2011-2014 OMICRON electronics GmbH |
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3 | * |
4 | * Based on da850evm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
7 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
9a3aae22 CR |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * Board | |
17 | */ | |
18 | #define CONFIG_DRIVER_TI_EMAC | |
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19 | #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN |
20 | ||
21 | /* | |
22 | * SoC Configuration | |
23 | */ | |
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24 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
25 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
26 | #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() | |
27 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
28 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
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29 | #define CONFIG_ARCH_CPU_INIT |
30 | #define CONFIG_DA8XX_GPIO | |
31 | #define CONFIG_HW_WATCHDOG | |
32 | #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE | |
33 | #define CONFIG_SYS_WDT_PERIOD_LOW \ | |
34 | (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ | |
35 | #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 | |
36 | #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) | |
37 | ||
38 | /* | |
39 | * PLL configuration | |
40 | */ | |
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41 | |
42 | #define CONFIG_SYS_DA850_PLL0_PLLM \ | |
43 | ((calimain_get_osc_freq() == 25000000) ? 23 : 24) | |
44 | #define CONFIG_SYS_DA850_PLL1_PLLM \ | |
45 | ((calimain_get_osc_freq() == 25000000) ? 20 : 21) | |
46 | ||
47 | /* | |
48 | * DDR2 memory configuration | |
49 | */ | |
50 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
51 | DV_DDR_PHY_EXT_STRBEN | \ | |
52 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
53 | ||
54 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
55 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ | |
56 | (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ | |
57 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
58 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
59 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
60 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
61 | (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
62 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
63 | ||
64 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
65 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
66 | ||
67 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
68 | (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
69 | (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
70 | (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
71 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
72 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
73 | (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
74 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
75 | (1 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
76 | ||
77 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
78 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
79 | (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
80 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
81 | (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
82 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
83 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
84 | (2 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
85 | ||
86 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF | |
87 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
88 | ||
89 | /* | |
90 | * Flash memory timing | |
91 | */ | |
92 | ||
93 | #define CONFIG_SYS_DA850_CS2CFG ( \ | |
94 | DAVINCI_ABCR_WSETUP(2) | \ | |
95 | DAVINCI_ABCR_WSTROBE(5) | \ | |
96 | DAVINCI_ABCR_WHOLD(3) | \ | |
97 | DAVINCI_ABCR_RSETUP(1) | \ | |
98 | DAVINCI_ABCR_RSTROBE(14) | \ | |
99 | DAVINCI_ABCR_RHOLD(0) | \ | |
100 | DAVINCI_ABCR_TA(3) | \ | |
101 | DAVINCI_ABCR_ASIZE_16BIT) | |
102 | ||
103 | /* single 64 MB NOR flash device connected to CS2 and CS3 */ | |
104 | #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG | |
105 | ||
106 | /* | |
107 | * Memory Info | |
108 | */ | |
109 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
110 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
111 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ | |
112 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
113 | ||
114 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
115 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
116 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
117 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
118 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
119 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
120 | ||
121 | /* memtest start addr */ | |
122 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
123 | ||
124 | /* memtest will be run on 16MB */ | |
125 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) | |
126 | ||
127 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
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128 | |
129 | /* | |
130 | * Serial Driver info | |
131 | */ | |
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132 | #define CONFIG_SYS_NS16550_SERIAL |
133 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
134 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
135 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
136 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
9a3aae22 | 137 | |
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138 | #define CONFIG_FLASH_CFI_DRIVER |
139 | #define CONFIG_SYS_FLASH_CFI | |
140 | #define CONFIG_SYS_FLASH_PROTECTION | |
141 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
142 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
143 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
144 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
145 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
146 | #define CONFIG_ENV_ADDR \ | |
147 | (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) | |
148 | #define CONFIG_ENV_SIZE (128 << 10) | |
149 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
150 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
151 | #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ | |
152 | #define CONFIG_SYS_MAX_FLASH_SECT \ | |
153 | ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) | |
154 | ||
155 | /* | |
156 | * Network & Ethernet Configuration | |
157 | */ | |
158 | #ifdef CONFIG_DRIVER_TI_EMAC | |
9a3aae22 | 159 | #define CONFIG_MII |
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160 | #define CONFIG_BOOTP_DNS2 |
161 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
162 | #define CONFIG_NET_RETRY_COUNT 10 | |
163 | #endif | |
164 | ||
165 | /* | |
166 | * U-Boot general configuration | |
167 | */ | |
168 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
9a3aae22 | 169 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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170 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
171 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
172 | #define CONFIG_LOADADDR 0xc0700000 | |
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173 | #define CONFIG_MX_CYCLIC |
174 | ||
175 | /* | |
176 | * Linux Information | |
177 | */ | |
178 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
179 | #define CONFIG_CMDLINE_TAG | |
180 | #define CONFIG_REVISION_TAG | |
181 | #define CONFIG_SETUP_MEMORY_TAGS | |
9a3aae22 | 182 | #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" |
9a3aae22 | 183 | #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ |
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184 | #define CONFIG_RESET_TO_RETRY |
185 | ||
186 | /* | |
187 | * Default environment settings | |
188 | * gpio0 = button, gpio1 = led green, gpio2 = led red | |
189 | * verify = n ... disable kernel checksum verification for faster booting | |
190 | */ | |
191 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
192 | "tftpdir=calimero\0" \ | |
193 | "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ | |
194 | "erase 0x60800000 +0x400000; " \ | |
195 | "cp.b $loadaddr 0x60800000 $filesize\0" \ | |
196 | "flashrootfs=" \ | |
197 | "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ | |
198 | "erase 0x60c00000 +0x2e00000; " \ | |
199 | "cp.b $loadaddr 0x60c00000 $filesize\0" \ | |
200 | "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ | |
201 | "protect off all; " \ | |
202 | "erase 0x60000000 +0x80000; " \ | |
203 | "cp.b $loadaddr 0x60000000 $filesize\0" \ | |
204 | "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ | |
205 | "erase 0x60080000 +0x780000; " \ | |
206 | "cp.b $loadaddr 0x60080000 $filesize\0" \ | |
207 | "erase_persistent=erase 0x63a00000 +0x600000;\0" \ | |
208 | "bootnor=setenv bootargs console=ttyS2,115200n8 " \ | |
209 | "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ | |
210 | "rootwait ethaddr=$ethaddr; " \ | |
211 | "gpio c 1; gpio s 2; bootm 0x60800000\0" \ | |
212 | "bootrlk=gpio s 1; gpio s 2;" \ | |
213 | "setenv bootargs console=ttyS2,115200n8 " \ | |
214 | "ethaddr=$ethaddr; bootm 0x60080000\0" \ | |
215 | "boottftp=setenv bootargs console=ttyS2,115200n8 " \ | |
216 | "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ | |
217 | "rootwait ethaddr=$ethaddr; " \ | |
218 | "tftpboot $loadaddr $tftpdir/uImage;" \ | |
219 | "gpio c 1; gpio s 2; bootm $loadaddr\0" \ | |
220 | "checkupdate=if test -n $update_flag; then " \ | |
221 | "echo Previous update failed - starting RLK; " \ | |
222 | "run bootrlk; fi; " \ | |
223 | "if test -n $initial_setup; then " \ | |
224 | "echo Running initial setup procedure; " \ | |
225 | "sleep 1; run flashall; fi\0" \ | |
226 | "product=accessory\0" \ | |
227 | "serial=XX12345\0" \ | |
228 | "checknor=" \ | |
229 | "if gpio i 0; then run bootnor; fi;\0" \ | |
230 | "checkrlk=" \ | |
231 | "if gpio i 0; then run bootrlk; fi;\0" \ | |
232 | "checkbutton=" \ | |
233 | "run checknor; sleep 1;" \ | |
234 | "run checknor; sleep 1;" \ | |
235 | "run checknor; sleep 1;" \ | |
236 | "run checknor; sleep 1;" \ | |
237 | "run checknor;" \ | |
238 | "gpio s 1; gpio s 2;" \ | |
239 | "echo ---- Release button to boot RLK ----;" \ | |
240 | "run checkrlk; sleep 1;" \ | |
241 | "run checkrlk; sleep 1;" \ | |
242 | "run checkrlk; sleep 1;" \ | |
243 | "run checkrlk; sleep 1;" \ | |
244 | "run checkrlk; sleep 1;" \ | |
245 | "run checkrlk;" \ | |
246 | "echo ---- Factory reset requested ----;" \ | |
247 | "gpio c 1;" \ | |
248 | "setenv factory_reset true;" \ | |
249 | "saveenv;" \ | |
250 | "run bootnor;\0" \ | |
251 | "flashall=run flashrlk;" \ | |
252 | "run flashkernel;" \ | |
253 | "run flashrootfs;" \ | |
254 | "setenv erase_datafs true;" \ | |
255 | "setenv initial_setup;" \ | |
256 | "saveenv;" \ | |
257 | "run bootnor;\0" \ | |
258 | "verify=n\0" \ | |
259 | "clearenv=protect off all;" \ | |
260 | "erase 0x60040000 +0x40000;\0" \ | |
261 | "bootlimit=3\0" \ | |
262 | "altbootcmd=run bootrlk\0" | |
263 | ||
264 | #define CONFIG_PREBOOT \ | |
265 | "echo Version: $ver; " \ | |
266 | "echo Serial: $serial; " \ | |
267 | "echo MAC: $ethaddr; " \ | |
268 | "echo Product: $product; " \ | |
269 | "gpio c 1; gpio c 2;" | |
270 | ||
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271 | /* additions for new relocation code, must added to all boards */ |
272 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
273 | /* initial stack pointer in internal SRAM */ | |
274 | #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) | |
275 | ||
0044c42e | 276 | #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ |
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277 | |
278 | #ifndef __ASSEMBLY__ | |
279 | int calimain_get_osc_freq(void); | |
280 | #endif | |
281 | ||
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282 | #include <asm/arch/hardware.h> |
283 | ||
9a3aae22 | 284 | #endif /* __CONFIG_H */ |