[people/ms/u-boot.git] / include / configs / canmb.h

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
#define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
#define CONFIG_DISPLAY_BOARDINFO

/*
 * allowed and functional CONFIG_SYS_TEXT_BASE values:
 * 0xfe000000	low boot at 0x00000100 (default board setting)
 * 0x00100000	RAM load and test
 */
#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP


/*
 * MUST be low boot - HIGHBOOT is not supported anymore
 */
#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#else
#   error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/canmb/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * Flash configuration, expect one 16 Megabyte Bank at most
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		(2*128*1024)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE       (128*1024)

/*
 * Memory map
 *
 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
 */
#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define	CONFIG_PHY_ADDR		0x0
/*
 * GPIO configuration:
 * PSC1,2,3 predefined as UART
 * PCI disabled
 * Ethernet 100 with MD
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058444

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047D01
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0x7f000000

#endif /* __CONFIG_H */
Commit	Line	Data
5e5f9ed2 WD	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5e5f9ed2 WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
b2a6dfe4	16	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
53677ef1	17	#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
ab9f5f83	18	#define CONFIG_DISPLAY_BOARDINFO
5e5f9ed2	19
2ae18241 WD	20	/*
	21	* allowed and functional CONFIG_SYS_TEXT_BASE values:
	22	* 0xfe000000 low boot at 0x00000100 (default board setting)
	23	* 0x00100000 RAM load and test
	24	*/
	25	#define CONFIG_SYS_TEXT_BASE 0xFE000000
	26
6d0f6bcf	27	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e5f9ed2	28
5e5f9ed2 WD	29	#define CONFIG_BOARD_EARLY_INIT_R
5e5f9ed2 WD	30
31d82672 BB	31	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	32
5e5f9ed2 WD	33	/*
	34	* Serial console configuration
	35	*/
	36	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	37	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	38	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e5f9ed2	39
37e4f24b	40
80ff4f99 JL	41	/*
	42	* BOOTP options
	43	*/
	44	#define CONFIG_BOOTP_BOOTFILESIZE
	45	#define CONFIG_BOOTP_BOOTPATH
	46	#define CONFIG_BOOTP_GATEWAY
	47	#define CONFIG_BOOTP_HOSTNAME
	48
	49
5e5f9ed2	50	/*
37e4f24b	51	* Command line configuration.
5e5f9ed2	52	*/
37e4f24b JL	53	#define CONFIG_CMD_ASKENV
	54	#define CONFIG_CMD_DATE
	55	#define CONFIG_CMD_DHCP
	56	#define CONFIG_CMD_IMMAP
	57	#define CONFIG_CMD_MII
37e4f24b JL	58	#define CONFIG_CMD_REGINFO
	59	#define CONFIG_CMD_SNTP
	60
5e5f9ed2 WD	61
	62	/*
	63	* MUST be low boot - HIGHBOOT is not supported anymore
	64	*/
14d0a02a	65	#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
6d0f6bcf JCPV	66	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	67	# define CONFIG_SYS_LOWBOOT16 1
5e5f9ed2	68	#else
14d0a02a	69	# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
5e5f9ed2 WD	70	#endif
	71
	72	/*
	73	* Autobooting
	74	*/
	75	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	76
	77	#define CONFIG_PREBOOT "echo;" \
32bf3d14	78	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5e5f9ed2 WD	79	"echo"
	80
	81	#undef CONFIG_BOOTARGS
	82
	83	#define CONFIG_EXTRA_ENV_SETTINGS \
	84	"netdev=eth0\0" \
	85	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	86	"nfsroot=${serverip}:${rootpath}\0" \
5e5f9ed2	87	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	88	"addip=setenv bootargs ${bootargs} " \
	89	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	90	":${hostname}:${netdev}:off panic=1\0" \
5e5f9ed2	91	"flash_nfs=run nfsargs addip;" \
fe126d8b	92	"bootm ${kernel_addr}\0" \
5e5f9ed2	93	"flash_self=run ramargs addip;" \
fe126d8b WD	94	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	95	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5e5f9ed2 WD	96	"rootpath=/opt/eldk/ppc_6xx\0" \
	97	"bootfile=/tftpboot/canmb/uImage\0" \
	98	""
	99
	100	#define CONFIG_BOOTCOMMAND "run flash_self"
	101
	102	/*
	103	* IPB Bus clocking configuration.
	104	*/
6d0f6bcf	105	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e5f9ed2 WD	106
	107	/*
	108	* Flash configuration, expect one 16 Megabyte Bank at most
	109	*/
6d0f6bcf JCPV	110	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	111	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	112	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
	113	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
5e5f9ed2	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	116	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e5f9ed2	117
00b1883a	118	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_EMPTY_INFO
5e5f9ed2	121
5e5f9ed2 WD	122	/*
	123	* Environment settings
	124	*/
5a1aceb0	125	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	126	#define CONFIG_ENV_OFFSET (21281024)
	127	#define CONFIG_ENV_SIZE 0x2000
	128	#define CONFIG_ENV_SECT_SIZE (128*1024)
5e5f9ed2 WD	129
	130	/*
	131	* Memory map
	132	*
	133	* Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
	134	*/
6d0f6bcf JCPV	135	#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
	136	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	137	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e5f9ed2 WD	138
5e5f9ed2 WD	139	/* Use SRAM until RAM will be available */
6d0f6bcf	140	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	141	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
5e5f9ed2 WD	142
5e5f9ed2 WD	143
25ddd1fb	144	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	145	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e5f9ed2	146
14d0a02a	147	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	148	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	149	# define CONFIG_SYS_RAMBOOT 1
5e5f9ed2 WD	150	#endif
5e5f9ed2 WD	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	153	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	154	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5e5f9ed2 WD	155
	156	/*
	157	* Ethernet configuration
	158	*/
	159	#define CONFIG_MPC5xxx_FEC 1
86321fc1	160	#define CONFIG_MPC5xxx_FEC_MII100
a6310928	161	#define CONFIG_PHY_ADDR 0x0
5e5f9ed2 WD	162	/*
	163	* GPIO configuration:
	164	* PSC1,2,3 predefined as UART
	165	* PCI disabled
	166	* Ethernet 100 with MD
	167	*/
6d0f6bcf	168	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444
5e5f9ed2 WD	169
	170	/*
	171	* Miscellaneous configurable options
	172	*/
6d0f6bcf	173	#define CONFIG_SYS_LONGHELP /* undef to save memory */
37e4f24b	174	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	175	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e5f9ed2	176	#else
6d0f6bcf	177	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e5f9ed2	178	#endif
6d0f6bcf JCPV	179	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	180	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	181	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e5f9ed2	182
6d0f6bcf JCPV	183	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	184	#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
5e5f9ed2	185
6d0f6bcf	186	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
5e5f9ed2	187
5e5f9ed2 WD	188	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
5e5f9ed2 WD	189
6d0f6bcf	190	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
37e4f24b	191	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	192	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
37e4f24b JL	193	#endif
37e4f24b JL	194
5e5f9ed2 WD	195	/*
	196	* Various low-level settings
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	199	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e5f9ed2	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	202	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	203	#define CONFIG_SYS_BOOTCS_CFG 0x00047D01
	204	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	205	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e5f9ed2	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	208	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e5f9ed2	209
6d0f6bcf	210	#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
5e5f9ed2 WD	211
5e5f9ed2 WD	212	#endif /* __CONFIG_H */