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9b75bad0 SL |
1 | /* |
2 | * | |
3 | * Congatec Conga-QEVAl board configuration file. | |
4 | * | |
5 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
6 | * Based on Freescale i.MX6Q Sabre Lite board configuration file. | |
7 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> | |
8 | * Leo Sartre, <lsartre@adeneo-embedded.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
9b75bad0 SL |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_CGTQMX6EVAL_H | |
14 | #define __CONFIG_CGTQMX6EVAL_H | |
15 | ||
9b75bad0 SL |
16 | #include "mx6_common.h" |
17 | ||
9b75bad0 SL |
18 | #define CONFIG_MACH_TYPE 4122 |
19 | ||
d7140351 OS |
20 | #ifdef CONFIG_SPL |
21 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
22 | #define CONFIG_SPL_MMC_SUPPORT | |
23 | #define CONFIG_SPL_SPI_SUPPORT | |
24 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
25 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) | |
26 | #define CONFIG_SPL_SPI_LOAD | |
27 | #include "imx6_spl.h" | |
28 | #endif | |
29 | ||
9b75bad0 SL |
30 | /* Size of malloc() pool */ |
31 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
32 | ||
33 | #define CONFIG_BOARD_EARLY_INIT_F | |
d7140351 | 34 | #define CONFIG_BOARD_LATE_INIT |
9b75bad0 | 35 | #define CONFIG_MISC_INIT_R |
9b75bad0 SL |
36 | |
37 | #define CONFIG_MXC_UART | |
38 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
39 | ||
40 | /* MMC Configs */ | |
9b75bad0 SL |
41 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
42 | ||
71bcdafe OS |
43 | /* SPI NOR */ |
44 | #define CONFIG_CMD_SF | |
45 | #define CONFIG_SPI_FLASH | |
46 | #define CONFIG_SPI_FLASH_STMICRO | |
47 | #define CONFIG_SPI_FLASH_SST | |
48 | #define CONFIG_MXC_SPI | |
49 | #define CONFIG_SF_DEFAULT_BUS 0 | |
50 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | |
51 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
52 | ||
9b75bad0 SL |
53 | /* Miscellaneous commands */ |
54 | #define CONFIG_CMD_BMODE | |
55 | ||
862187b7 | 56 | /* Thermal support */ |
1368f993 | 57 | #define CONFIG_IMX_THERMAL |
862187b7 | 58 | |
4c9929d6 OS |
59 | /* I2C Configs */ |
60 | #define CONFIG_CMD_I2C | |
61 | #define CONFIG_SYS_I2C | |
62 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
63 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
64 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
4c9929d6 OS |
65 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
66 | #define CONFIG_SYS_I2C_SPEED 100000 | |
67 | ||
68 | /* PMIC */ | |
69 | #define CONFIG_POWER | |
70 | #define CONFIG_POWER_I2C | |
71 | #define CONFIG_POWER_PFUZE100 | |
72 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
73 | ||
95246ac7 OS |
74 | /* USB Configs */ |
75 | #define CONFIG_CMD_USB | |
76 | #define CONFIG_CMD_FAT | |
77 | #define CONFIG_USB_EHCI | |
78 | #define CONFIG_USB_EHCI_MX6 | |
79 | #define CONFIG_USB_STORAGE | |
80 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
81 | #define CONFIG_USB_HOST_ETHER | |
82 | #define CONFIG_USB_ETHER_ASIX | |
83 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
84 | #define CONFIG_MXC_USB_FLAGS 0 | |
85 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ | |
86 | #define CONFIG_USB_KEYBOARD | |
87 | #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP | |
88 | ||
3e08e1b7 OS |
89 | #define CONFIG_CI_UDC |
90 | #define CONFIG_USBD_HS | |
91 | #define CONFIG_USB_GADGET_DUALSPEED | |
92 | ||
93 | #define CONFIG_USB_GADGET | |
94 | #define CONFIG_CMD_USB_MASS_STORAGE | |
95 | #define CONFIG_USB_FUNCTION_MASS_STORAGE | |
96 | #define CONFIG_USB_GADGET_DOWNLOAD | |
97 | #define CONFIG_USB_GADGET_VBUS_DRAW 2 | |
98 | ||
99 | #define CONFIG_G_DNL_VENDOR_NUM 0x0525 | |
100 | #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 | |
101 | #define CONFIG_G_DNL_MANUFACTURER "Congatec" | |
102 | ||
e0a352d1 OS |
103 | /* USB Device Firmware Update support */ |
104 | #define CONFIG_CMD_DFU | |
105 | #define CONFIG_USB_FUNCTION_DFU | |
106 | #define CONFIG_DFU_MMC | |
107 | #define CONFIG_DFU_SF | |
108 | ||
eb76f13a OS |
109 | #define CONFIG_USB_FUNCTION_FASTBOOT |
110 | #define CONFIG_CMD_FASTBOOT | |
111 | #define CONFIG_ANDROID_BOOT_IMAGE | |
112 | #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR | |
113 | #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 | |
114 | ||
6d551f27 OS |
115 | /* Framebuffer */ |
116 | #define CONFIG_VIDEO | |
117 | #define CONFIG_VIDEO_IPUV3 | |
118 | #define CONFIG_CFB_CONSOLE | |
119 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
120 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
121 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
122 | #define CONFIG_VIDEO_BMP_RLE8 | |
123 | #define CONFIG_SPLASH_SCREEN | |
124 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
125 | #define CONFIG_BMP_16BPP | |
126 | #define CONFIG_VIDEO_LOGO | |
127 | #define CONFIG_VIDEO_BMP_LOGO | |
128 | #ifdef CONFIG_MX6DL | |
129 | #define CONFIG_IPUV3_CLK 198000000 | |
130 | #else | |
131 | #define CONFIG_IPUV3_CLK 264000000 | |
132 | #endif | |
133 | #define CONFIG_IMX_HDMI | |
134 | ||
6731bc8d OS |
135 | /* SATA */ |
136 | #define CONFIG_CMD_SATA | |
137 | #define CONFIG_DWC_AHSATA | |
138 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
139 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
140 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
141 | #define CONFIG_LBA48 | |
142 | #define CONFIG_LIBATA | |
143 | ||
f0222902 OS |
144 | /* Ethernet */ |
145 | #define CONFIG_CMD_PING | |
146 | #define CONFIG_CMD_DHCP | |
147 | #define CONFIG_CMD_MII | |
148 | #define CONFIG_FEC_MXC | |
149 | #define CONFIG_MII | |
150 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
151 | #define CONFIG_FEC_XCV_TYPE RGMII | |
152 | #define CONFIG_ETHPRIME "FEC" | |
153 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
154 | #define CONFIG_PHYLIB | |
155 | #define CONFIG_PHY_ATHEROS | |
156 | ||
5b94ce2c OS |
157 | /* Command definition */ |
158 | ||
159 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
160 | #define CONFIG_CONSOLE_DEV "ttymxc1" | |
161 | #define CONFIG_MMCROOT "/dev/mmcblk0p2" | |
162 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
9b75bad0 | 163 | |
d7140351 | 164 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
9b75bad0 SL |
165 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
166 | "script=boot.scr\0" \ | |
4ac0c2bf | 167 | "image=zImage\0" \ |
d7140351 | 168 | "fdtfile=undefined\0" \ |
5b94ce2c | 169 | "fdt_addr_r=0x18000000\0" \ |
9b75bad0 | 170 | "boot_fdt=try\0" \ |
5b94ce2c OS |
171 | "ip_dyn=yes\0" \ |
172 | "console=" CONFIG_CONSOLE_DEV "\0" \ | |
e0a352d1 OS |
173 | "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ |
174 | "dfu_alt_info_spl=spl raw 0x400\0" \ | |
175 | "dfu_alt_info_img=u-boot raw 0x10000\0" \ | |
176 | "dfu_alt_info=spl raw 0x400\0" \ | |
5b94ce2c OS |
177 | "bootm_size=0x10000000\0" \ |
178 | "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ | |
9b75bad0 | 179 | "mmcpart=1\0" \ |
5b94ce2c OS |
180 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
181 | "update_sd_firmware=" \ | |
182 | "if test ${ip_dyn} = yes; then " \ | |
183 | "setenv get_cmd dhcp; " \ | |
184 | "else " \ | |
185 | "setenv get_cmd tftp; " \ | |
186 | "fi; " \ | |
187 | "if mmc dev ${mmcdev}; then " \ | |
188 | "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
189 | "setexpr fw_sz ${filesize} / 0x200; " \ | |
190 | "setexpr fw_sz ${fw_sz} + 1; " \ | |
191 | "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
192 | "fi; " \ | |
193 | "fi\0" \ | |
9b75bad0 SL |
194 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
195 | "root=${mmcroot}\0" \ | |
196 | "loadbootscript=" \ | |
5b94ce2c | 197 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
9b75bad0 SL |
198 | "bootscript=echo Running bootscript from mmc ...; " \ |
199 | "source\0" \ | |
5b94ce2c OS |
200 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
201 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ | |
9b75bad0 SL |
202 | "mmcboot=echo Booting from mmc ...; " \ |
203 | "run mmcargs; " \ | |
204 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
205 | "if run loadfdt; then " \ | |
5b94ce2c OS |
206 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ |
207 | "else " \ | |
208 | "if test ${boot_fdt} = try; then " \ | |
209 | "bootz; " \ | |
210 | "else " \ | |
211 | "echo WARN: Cannot load the DT; " \ | |
212 | "fi; " \ | |
213 | "fi; " \ | |
214 | "else " \ | |
215 | "bootz; " \ | |
216 | "fi;\0" \ | |
d7140351 OS |
217 | "findfdt="\ |
218 | "if test $board_rev = MX6Q ; then " \ | |
219 | "setenv fdtfile imx6q-qmx6.dtb; fi; " \ | |
220 | "if test $board_rev = MX6DL ; then " \ | |
221 | "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ | |
222 | "if test $fdtfile = undefined; then " \ | |
223 | "echo WARNING: Could not determine dtb to use; fi; \0" \ | |
5b94ce2c OS |
224 | "netargs=setenv bootargs console=${console},${baudrate} " \ |
225 | "root=/dev/nfs " \ | |
226 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
227 | "netboot=echo Booting from net ...; " \ | |
228 | "run netargs; " \ | |
229 | "if test ${ip_dyn} = yes; then " \ | |
230 | "setenv get_cmd dhcp; " \ | |
231 | "else " \ | |
232 | "setenv get_cmd tftp; " \ | |
233 | "fi; " \ | |
234 | "${get_cmd} ${image}; " \ | |
235 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
236 | "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ | |
237 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ | |
9b75bad0 SL |
238 | "else " \ |
239 | "if test ${boot_fdt} = try; then " \ | |
4ac0c2bf | 240 | "bootz; " \ |
9b75bad0 SL |
241 | "else " \ |
242 | "echo WARN: Cannot load the DT; " \ | |
243 | "fi; " \ | |
244 | "fi; " \ | |
245 | "else " \ | |
4ac0c2bf | 246 | "bootz; " \ |
5b94ce2c | 247 | "fi;\0" \ |
71bcdafe | 248 | "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ |
9b75bad0 SL |
249 | |
250 | #define CONFIG_BOOTCOMMAND \ | |
71bcdafe | 251 | "run spilock;" \ |
d7140351 | 252 | "run findfdt; " \ |
5b94ce2c OS |
253 | "mmc dev ${mmcdev};" \ |
254 | "if mmc rescan; then " \ | |
255 | "if run loadbootscript; then " \ | |
256 | "run bootscript; " \ | |
257 | "else " \ | |
258 | "if run loadimage; then " \ | |
259 | "run mmcboot; " \ | |
260 | "else run netboot; " \ | |
261 | "fi; " \ | |
262 | "fi; " \ | |
263 | "else run netboot; fi" | |
9b75bad0 | 264 | |
9b75bad0 SL |
265 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
266 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
267 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
268 | ||
9b75bad0 SL |
269 | /* Physical Memory Map */ |
270 | #define CONFIG_NR_DRAM_BANKS 1 | |
271 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
272 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
273 | ||
274 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
275 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
276 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
277 | ||
278 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
279 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
280 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
281 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
282 | ||
056845c2 | 283 | /* Environment organization */ |
d5de9108 | 284 | #if defined (CONFIG_ENV_IS_IN_MMC) |
9b75bad0 SL |
285 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
286 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
d5de9108 OS |
287 | #endif |
288 | ||
289 | #define CONFIG_ENV_SIZE (8 * 1024) | |
290 | ||
291 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
292 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
293 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
294 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
295 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
296 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
297 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
298 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
299 | #endif | |
9b75bad0 | 300 | |
9b75bad0 | 301 | #endif /* __CONFIG_CGTQMX6EVAL_H */ |