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Commit | Line | Data |
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9b75bad0 SL |
1 | /* |
2 | * | |
3 | * Congatec Conga-QEVAl board configuration file. | |
4 | * | |
5 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
6 | * Based on Freescale i.MX6Q Sabre Lite board configuration file. | |
7 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> | |
8 | * Leo Sartre, <lsartre@adeneo-embedded.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
9b75bad0 SL |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_CGTQMX6EVAL_H | |
14 | #define __CONFIG_CGTQMX6EVAL_H | |
15 | ||
9b75bad0 SL |
16 | #include "mx6_common.h" |
17 | ||
9b75bad0 SL |
18 | #define CONFIG_MACH_TYPE 4122 |
19 | ||
d7140351 | 20 | #ifdef CONFIG_SPL |
d7140351 OS |
21 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) |
22 | #define CONFIG_SPL_SPI_LOAD | |
23 | #include "imx6_spl.h" | |
24 | #endif | |
25 | ||
9b75bad0 SL |
26 | /* Size of malloc() pool */ |
27 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
28 | ||
9b75bad0 | 29 | #define CONFIG_MISC_INIT_R |
9b75bad0 SL |
30 | |
31 | #define CONFIG_MXC_UART | |
32 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
33 | ||
34 | /* MMC Configs */ | |
9b75bad0 SL |
35 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
36 | ||
71bcdafe | 37 | /* SPI NOR */ |
71bcdafe OS |
38 | #define CONFIG_SPI_FLASH |
39 | #define CONFIG_SPI_FLASH_STMICRO | |
40 | #define CONFIG_SPI_FLASH_SST | |
71bcdafe OS |
41 | #define CONFIG_SF_DEFAULT_BUS 0 |
42 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | |
43 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
44 | ||
862187b7 | 45 | /* Thermal support */ |
1368f993 | 46 | #define CONFIG_IMX_THERMAL |
862187b7 | 47 | |
4c9929d6 | 48 | /* I2C Configs */ |
4c9929d6 OS |
49 | #define CONFIG_SYS_I2C |
50 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
51 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
52 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
4c9929d6 OS |
53 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
54 | #define CONFIG_SYS_I2C_SPEED 100000 | |
55 | ||
56 | /* PMIC */ | |
57 | #define CONFIG_POWER | |
58 | #define CONFIG_POWER_I2C | |
59 | #define CONFIG_POWER_PFUZE100 | |
60 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
61 | ||
95246ac7 | 62 | /* USB Configs */ |
95246ac7 | 63 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
95246ac7 OS |
64 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
65 | #define CONFIG_MXC_USB_FLAGS 0 | |
66 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ | |
95246ac7 | 67 | |
3e08e1b7 | 68 | #define CONFIG_USBD_HS |
3e08e1b7 | 69 | |
6d551f27 | 70 | /* Framebuffer */ |
6d551f27 | 71 | #define CONFIG_VIDEO_IPUV3 |
6d551f27 OS |
72 | #define CONFIG_VIDEO_BMP_RLE8 |
73 | #define CONFIG_SPLASH_SCREEN | |
74 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
75 | #define CONFIG_BMP_16BPP | |
76 | #define CONFIG_VIDEO_LOGO | |
77 | #define CONFIG_VIDEO_BMP_LOGO | |
6d551f27 OS |
78 | #define CONFIG_IMX_HDMI |
79 | ||
6731bc8d | 80 | /* SATA */ |
6731bc8d OS |
81 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
82 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
83 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
84 | #define CONFIG_LBA48 | |
6731bc8d | 85 | |
f0222902 | 86 | /* Ethernet */ |
f0222902 OS |
87 | #define CONFIG_FEC_MXC |
88 | #define CONFIG_MII | |
89 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
90 | #define CONFIG_FEC_XCV_TYPE RGMII | |
91 | #define CONFIG_ETHPRIME "FEC" | |
92 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
f0222902 OS |
93 | #define CONFIG_PHY_ATHEROS |
94 | ||
5b94ce2c OS |
95 | /* Command definition */ |
96 | ||
97 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
12ca05a3 | 98 | #define CONSOLE_DEV "ttymxc1" |
5b94ce2c OS |
99 | #define CONFIG_MMCROOT "/dev/mmcblk0p2" |
100 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
9b75bad0 | 101 | |
d7140351 | 102 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
9b75bad0 SL |
103 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
104 | "script=boot.scr\0" \ | |
4ac0c2bf | 105 | "image=zImage\0" \ |
d7140351 | 106 | "fdtfile=undefined\0" \ |
5b94ce2c | 107 | "fdt_addr_r=0x18000000\0" \ |
9b75bad0 | 108 | "boot_fdt=try\0" \ |
5b94ce2c | 109 | "ip_dyn=yes\0" \ |
12ca05a3 | 110 | "console=" CONSOLE_DEV "\0" \ |
e0a352d1 OS |
111 | "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ |
112 | "dfu_alt_info_spl=spl raw 0x400\0" \ | |
113 | "dfu_alt_info_img=u-boot raw 0x10000\0" \ | |
114 | "dfu_alt_info=spl raw 0x400\0" \ | |
5b94ce2c OS |
115 | "bootm_size=0x10000000\0" \ |
116 | "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ | |
9b75bad0 | 117 | "mmcpart=1\0" \ |
5b94ce2c OS |
118 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
119 | "update_sd_firmware=" \ | |
120 | "if test ${ip_dyn} = yes; then " \ | |
121 | "setenv get_cmd dhcp; " \ | |
122 | "else " \ | |
123 | "setenv get_cmd tftp; " \ | |
124 | "fi; " \ | |
125 | "if mmc dev ${mmcdev}; then " \ | |
126 | "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
127 | "setexpr fw_sz ${filesize} / 0x200; " \ | |
128 | "setexpr fw_sz ${fw_sz} + 1; " \ | |
129 | "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
130 | "fi; " \ | |
131 | "fi\0" \ | |
9b75bad0 SL |
132 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
133 | "root=${mmcroot}\0" \ | |
134 | "loadbootscript=" \ | |
5b94ce2c | 135 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
9b75bad0 SL |
136 | "bootscript=echo Running bootscript from mmc ...; " \ |
137 | "source\0" \ | |
5b94ce2c OS |
138 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
139 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ | |
9b75bad0 SL |
140 | "mmcboot=echo Booting from mmc ...; " \ |
141 | "run mmcargs; " \ | |
142 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
143 | "if run loadfdt; then " \ | |
5b94ce2c OS |
144 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ |
145 | "else " \ | |
146 | "if test ${boot_fdt} = try; then " \ | |
147 | "bootz; " \ | |
148 | "else " \ | |
149 | "echo WARN: Cannot load the DT; " \ | |
150 | "fi; " \ | |
151 | "fi; " \ | |
152 | "else " \ | |
153 | "bootz; " \ | |
154 | "fi;\0" \ | |
d7140351 OS |
155 | "findfdt="\ |
156 | "if test $board_rev = MX6Q ; then " \ | |
157 | "setenv fdtfile imx6q-qmx6.dtb; fi; " \ | |
158 | "if test $board_rev = MX6DL ; then " \ | |
159 | "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ | |
160 | "if test $fdtfile = undefined; then " \ | |
161 | "echo WARNING: Could not determine dtb to use; fi; \0" \ | |
5b94ce2c OS |
162 | "netargs=setenv bootargs console=${console},${baudrate} " \ |
163 | "root=/dev/nfs " \ | |
164 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
165 | "netboot=echo Booting from net ...; " \ | |
166 | "run netargs; " \ | |
167 | "if test ${ip_dyn} = yes; then " \ | |
168 | "setenv get_cmd dhcp; " \ | |
169 | "else " \ | |
170 | "setenv get_cmd tftp; " \ | |
171 | "fi; " \ | |
172 | "${get_cmd} ${image}; " \ | |
173 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
174 | "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ | |
175 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ | |
9b75bad0 SL |
176 | "else " \ |
177 | "if test ${boot_fdt} = try; then " \ | |
4ac0c2bf | 178 | "bootz; " \ |
9b75bad0 SL |
179 | "else " \ |
180 | "echo WARN: Cannot load the DT; " \ | |
181 | "fi; " \ | |
182 | "fi; " \ | |
183 | "else " \ | |
4ac0c2bf | 184 | "bootz; " \ |
5b94ce2c | 185 | "fi;\0" \ |
71bcdafe | 186 | "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ |
9b75bad0 SL |
187 | |
188 | #define CONFIG_BOOTCOMMAND \ | |
71bcdafe | 189 | "run spilock;" \ |
d7140351 | 190 | "run findfdt; " \ |
5b94ce2c OS |
191 | "mmc dev ${mmcdev};" \ |
192 | "if mmc rescan; then " \ | |
193 | "if run loadbootscript; then " \ | |
194 | "run bootscript; " \ | |
195 | "else " \ | |
196 | "if run loadimage; then " \ | |
197 | "run mmcboot; " \ | |
198 | "else run netboot; " \ | |
199 | "fi; " \ | |
200 | "fi; " \ | |
201 | "else run netboot; fi" | |
9b75bad0 | 202 | |
9b75bad0 SL |
203 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
204 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
205 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
206 | ||
9b75bad0 SL |
207 | /* Physical Memory Map */ |
208 | #define CONFIG_NR_DRAM_BANKS 1 | |
209 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
9b75bad0 SL |
210 | |
211 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
212 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
213 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
214 | ||
215 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
216 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
217 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
218 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
219 | ||
056845c2 | 220 | /* Environment organization */ |
d5de9108 | 221 | #if defined (CONFIG_ENV_IS_IN_MMC) |
9b75bad0 SL |
222 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
223 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
d5de9108 OS |
224 | #endif |
225 | ||
226 | #define CONFIG_ENV_SIZE (8 * 1024) | |
227 | ||
d5de9108 OS |
228 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) |
229 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
230 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
231 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
232 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
233 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
234 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
235 | #endif | |
9b75bad0 | 236 | |
9b75bad0 | 237 | #endif /* __CONFIG_CGTQMX6EVAL_H */ |