[people/ms/u-boot.git] / include / configs / cgtqmx6eval.h

/*
 *
 * Congatec Conga-QEVAl board configuration file.
 *
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 * Based on Freescale i.MX6Q Sabre Lite board configuration file.
 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
 * Leo Sartre, <lsartre@adeneo-embedded.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CGTQMX6EVAL_H
#define __CONFIG_CGTQMX6EVAL_H

#include "mx6_common.h"

#define CONFIG_MACH_TYPE	4122

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	       UART2_BASE

/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR      0

/* Miscellaneous commands */
#define CONFIG_CMD_BMODE

/* Thermal support */
#define CONFIG_IMX_THERMAL

/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED		  100000

/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08

/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS	0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP

#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED

#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW	2

#define CONFIG_G_DNL_VENDOR_NUM		0x0525
#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
#define CONFIG_G_DNL_MANUFACTURER	"Congatec"

/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#ifdef CONFIG_MX6DL
#define CONFIG_IPUV3_CLK 198000000
#else
#define CONFIG_IPUV3_CLK 264000000
#endif
#define CONFIG_IMX_HDMI

/* SATA */
#define CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_DWC_AHSATA_PORT_ID	0
#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA

/* Ethernet */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RGMII
#define CONFIG_ETHPRIME			"FEC"
#define CONFIG_FEC_MXC_PHYADDR		6
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

/* Command definition */

#define CONFIG_MXC_UART_BASE	UART2_BASE
#define CONFIG_CONSOLE_DEV	"ttymxc1"
#define CONFIG_MMCROOT		"/dev/mmcblk0p2"
#define CONFIG_SYS_MMC_ENV_DEV		0

#define CONFIG_EXTRA_ENV_SETTINGS \
	"script=boot.scr\0" \
	"image=zImage\0" \
	"fdtfile=imx6q-qmx6.dtb\0" \
	"fdt_addr_r=0x18000000\0" \
	"boot_fdt=try\0" \
	"ip_dyn=yes\0" \
	"console=" CONFIG_CONSOLE_DEV "\0" \
	"bootm_size=0x10000000\0" \
	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
	"mmcpart=1\0" \
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	"update_sd_firmware=" \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"if mmc dev ${mmcdev}; then "	\
			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
				"setexpr fw_sz ${filesize} / 0x200; " \
				"setexpr fw_sz ${fw_sz} + 1; "	\
				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
			"fi; "	\
		"fi\0" \
	"mmcargs=setenv bootargs console=${console},${baudrate} " \
		"root=${mmcroot}\0" \
	"loadbootscript=" \
		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
			"if run loadfdt; then " \
				"bootz ${loadaddr} - ${fdt_addr_r}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo WARN: Cannot load the DT; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0" \
	"netargs=setenv bootargs console=${console},${baudrate} " \
		"root=/dev/nfs " \
		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	"netboot=echo Booting from net ...; " \
		"run netargs; " \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"${get_cmd} ${image}; " \
		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
				"bootz ${loadaddr} - ${fdt_addr_r}; " \
			"else " \
				"if test ${boot_fdt} = try; then " \
					"bootz; " \
				"else " \
					"echo WARN: Cannot load the DT; " \
				"fi; " \
			"fi; " \
		"else " \
			"bootz; " \
		"fi;\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev};" \
	"if mmc rescan; then " \
		"if run loadbootscript; then " \
		"run bootscript; " \
		"else " \
			"if run loadimage; then " \
				"run mmcboot; " \
			"else run netboot; " \
			"fi; " \
		"fi; " \
	"else run netboot; fi"

#define CONFIG_SYS_MEMTEST_START       0x10000000
#define CONFIG_SYS_MEMTEST_END	       0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS	       1
#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* Environment organization */
#define CONFIG_ENV_SIZE			(8 * 1024)

#define CONFIG_ENV_IS_IN_MMC

#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0

#endif			       /* __CONFIG_CGTQMX6EVAL_H */
Commit	Line	Data
9b75bad0 SL	1	/*
	2	*
	3	* Congatec Conga-QEVAl board configuration file.
	4	*
	5	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	6	* Based on Freescale i.MX6Q Sabre Lite board configuration file.
	7	* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
	8	* Leo Sartre, <lsartre@adeneo-embedded.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
9b75bad0 SL	11	*/
	12
	13	#ifndef __CONFIG_CGTQMX6EVAL_H
	14	#define __CONFIG_CGTQMX6EVAL_H
	15
9b75bad0 SL	16	#include "mx6_common.h"
9b75bad0 SL	17
9b75bad0 SL	18	#define CONFIG_MACH_TYPE 4122
9b75bad0 SL	19
9b75bad0 SL	20	/* Size of malloc() pool */
	21	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	22
	23	#define CONFIG_BOARD_EARLY_INIT_F
	24	#define CONFIG_MISC_INIT_R
9b75bad0 SL	25
	26	#define CONFIG_MXC_UART
	27	#define CONFIG_MXC_UART_BASE UART2_BASE
	28
	29	/* MMC Configs */
9b75bad0 SL	30	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
9b75bad0 SL	31
9b75bad0 SL	32	/* Miscellaneous commands */
	33	#define CONFIG_CMD_BMODE
	34
862187b7	35	/* Thermal support */
1368f993	36	#define CONFIG_IMX_THERMAL
862187b7	37
4c9929d6 OS	38	/* I2C Configs */
	39	#define CONFIG_CMD_I2C
	40	#define CONFIG_SYS_I2C
	41	#define CONFIG_SYS_I2C_MXC
03544c66 AA	42	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	43	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
4c9929d6 OS	44	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	45	#define CONFIG_SYS_I2C_SPEED 100000
	46
	47	/* PMIC */
	48	#define CONFIG_POWER
	49	#define CONFIG_POWER_I2C
	50	#define CONFIG_POWER_PFUZE100
	51	#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
	52
95246ac7 OS	53	/* USB Configs */
	54	#define CONFIG_CMD_USB
	55	#define CONFIG_CMD_FAT
	56	#define CONFIG_USB_EHCI
	57	#define CONFIG_USB_EHCI_MX6
	58	#define CONFIG_USB_STORAGE
	59	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	60	#define CONFIG_USB_HOST_ETHER
	61	#define CONFIG_USB_ETHER_ASIX
	62	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	63	#define CONFIG_MXC_USB_FLAGS 0
	64	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
	65	#define CONFIG_USB_KEYBOARD
	66	#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
	67
3e08e1b7 OS	68	#define CONFIG_CI_UDC
	69	#define CONFIG_USBD_HS
	70	#define CONFIG_USB_GADGET_DUALSPEED
	71
	72	#define CONFIG_USB_GADGET
	73	#define CONFIG_CMD_USB_MASS_STORAGE
	74	#define CONFIG_USB_FUNCTION_MASS_STORAGE
	75	#define CONFIG_USB_GADGET_DOWNLOAD
	76	#define CONFIG_USB_GADGET_VBUS_DRAW 2
	77
	78	#define CONFIG_G_DNL_VENDOR_NUM 0x0525
	79	#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
	80	#define CONFIG_G_DNL_MANUFACTURER "Congatec"
	81
6d551f27 OS	82	/* Framebuffer */
	83	#define CONFIG_VIDEO
	84	#define CONFIG_VIDEO_IPUV3
	85	#define CONFIG_CFB_CONSOLE
	86	#define CONFIG_VGA_AS_SINGLE_DEVICE
	87	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	88	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	89	#define CONFIG_VIDEO_BMP_RLE8
	90	#define CONFIG_SPLASH_SCREEN
	91	#define CONFIG_SPLASH_SCREEN_ALIGN
	92	#define CONFIG_BMP_16BPP
	93	#define CONFIG_VIDEO_LOGO
	94	#define CONFIG_VIDEO_BMP_LOGO
	95	#ifdef CONFIG_MX6DL
	96	#define CONFIG_IPUV3_CLK 198000000
	97	#else
	98	#define CONFIG_IPUV3_CLK 264000000
	99	#endif
	100	#define CONFIG_IMX_HDMI
	101
6731bc8d OS	102	/* SATA */
	103	#define CONFIG_CMD_SATA
	104	#define CONFIG_DWC_AHSATA
	105	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	106	#define CONFIG_DWC_AHSATA_PORT_ID 0
	107	#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	108	#define CONFIG_LBA48
	109	#define CONFIG_LIBATA
	110
f0222902 OS	111	/* Ethernet */
	112	#define CONFIG_CMD_PING
	113	#define CONFIG_CMD_DHCP
	114	#define CONFIG_CMD_MII
	115	#define CONFIG_FEC_MXC
	116	#define CONFIG_MII
	117	#define IMX_FEC_BASE ENET_BASE_ADDR
	118	#define CONFIG_FEC_XCV_TYPE RGMII
	119	#define CONFIG_ETHPRIME "FEC"
	120	#define CONFIG_FEC_MXC_PHYADDR 6
	121	#define CONFIG_PHYLIB
	122	#define CONFIG_PHY_ATHEROS
	123
5b94ce2c OS	124	/* Command definition */
	125
	126	#define CONFIG_MXC_UART_BASE UART2_BASE
	127	#define CONFIG_CONSOLE_DEV "ttymxc1"
	128	#define CONFIG_MMCROOT "/dev/mmcblk0p2"
	129	#define CONFIG_SYS_MMC_ENV_DEV 0
9b75bad0 SL	130
	131	#define CONFIG_EXTRA_ENV_SETTINGS \
	132	"script=boot.scr\0" \
4ac0c2bf	133	"image=zImage\0" \
5b94ce2c OS	134	"fdtfile=imx6q-qmx6.dtb\0" \
5b94ce2c OS	135	"fdt_addr_r=0x18000000\0" \
9b75bad0	136	"boot_fdt=try\0" \
5b94ce2c OS	137	"ip_dyn=yes\0" \
	138	"console=" CONFIG_CONSOLE_DEV "\0" \
	139	"bootm_size=0x10000000\0" \
	140	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
9b75bad0	141	"mmcpart=1\0" \
5b94ce2c OS	142	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	143	"update_sd_firmware=" \
	144	"if test ${ip_dyn} = yes; then " \
	145	"setenv get_cmd dhcp; " \
	146	"else " \
	147	"setenv get_cmd tftp; " \
	148	"fi; " \
	149	"if mmc dev ${mmcdev}; then " \
	150	"if ${get_cmd} ${update_sd_firmware_filename}; then " \
	151	"setexpr fw_sz ${filesize} / 0x200; " \
	152	"setexpr fw_sz ${fw_sz} + 1; " \
	153	"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
	154	"fi; " \
	155	"fi\0" \
9b75bad0 SL	156	"mmcargs=setenv bootargs console=${console},${baudrate} " \
	157	"root=${mmcroot}\0" \
	158	"loadbootscript=" \
5b94ce2c	159	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
9b75bad0 SL	160	"bootscript=echo Running bootscript from mmc ...; " \
9b75bad0 SL	161	"source\0" \
5b94ce2c OS	162	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
5b94ce2c OS	163	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
9b75bad0 SL	164	"mmcboot=echo Booting from mmc ...; " \
	165	"run mmcargs; " \
	166	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	167	"if run loadfdt; then " \
5b94ce2c OS	168	"bootz ${loadaddr} - ${fdt_addr_r}; " \
	169	"else " \
	170	"if test ${boot_fdt} = try; then " \
	171	"bootz; " \
	172	"else " \
	173	"echo WARN: Cannot load the DT; " \
	174	"fi; " \
	175	"fi; " \
	176	"else " \
	177	"bootz; " \
	178	"fi;\0" \
	179	"netargs=setenv bootargs console=${console},${baudrate} " \
	180	"root=/dev/nfs " \
	181	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	182	"netboot=echo Booting from net ...; " \
	183	"run netargs; " \
	184	"if test ${ip_dyn} = yes; then " \
	185	"setenv get_cmd dhcp; " \
	186	"else " \
	187	"setenv get_cmd tftp; " \
	188	"fi; " \
	189	"${get_cmd} ${image}; " \
	190	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	191	"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
	192	"bootz ${loadaddr} - ${fdt_addr_r}; " \
9b75bad0 SL	193	"else " \
9b75bad0 SL	194	"if test ${boot_fdt} = try; then " \
4ac0c2bf	195	"bootz; " \
9b75bad0 SL	196	"else " \
	197	"echo WARN: Cannot load the DT; " \
	198	"fi; " \
	199	"fi; " \
	200	"else " \
4ac0c2bf	201	"bootz; " \
5b94ce2c	202	"fi;\0" \
9b75bad0 SL	203
9b75bad0 SL	204	#define CONFIG_BOOTCOMMAND \
5b94ce2c OS	205	"mmc dev ${mmcdev};" \
	206	"if mmc rescan; then " \
	207	"if run loadbootscript; then " \
	208	"run bootscript; " \
	209	"else " \
	210	"if run loadimage; then " \
	211	"run mmcboot; " \
	212	"else run netboot; " \
	213	"fi; " \
	214	"fi; " \
	215	"else run netboot; fi"
9b75bad0	216
9b75bad0 SL	217	#define CONFIG_SYS_MEMTEST_START 0x10000000
	218	#define CONFIG_SYS_MEMTEST_END 0x10010000
	219	#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
	220
9b75bad0 SL	221	/* Physical Memory Map */
	222	#define CONFIG_NR_DRAM_BANKS 1
	223	#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	224	#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
	225
	226	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	227	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	228	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	229
	230	#define CONFIG_SYS_INIT_SP_OFFSET \
	231	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	232	#define CONFIG_SYS_INIT_SP_ADDR \
	233	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	234
056845c2	235	/* Environment organization */
9b75bad0 SL	236	#define CONFIG_ENV_SIZE (8 * 1024)
	237
	238	#define CONFIG_ENV_IS_IN_MMC
	239
	240	#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
	241	#define CONFIG_SYS_MMC_ENV_DEV 0
	242
9b75bad0	243	#endif /* __CONFIG_CGTQMX6EVAL_H */