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8ef07571 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2008 | |
4 | * Graeme Russ, graeme.russ@gmail.com. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | #include <configs/x86-common.h> | |
17 | ||
18 | #define CONFIG_SYS_CAR_ADDR 0xff7e0000 | |
19 | #define CONFIG_SYS_CAR_SIZE (128 * 1024) | |
20 | #define CONFIG_SYS_MONITOR_LEN (1 << 20) | |
65dd74a6 | 21 | #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 |
fce7b276 | 22 | #define CONFIG_SYS_X86_START16 0xfffff800 |
437c2b7c | 23 | #define CONFIG_BOARD_EARLY_INIT_F |
65dd74a6 | 24 | #define CONFIG_DISPLAY_CPUINFO |
8ef07571 | 25 | |
fce7b276 | 26 | #define CONFIG_X86_RESET_VECTOR |
8ef07571 | 27 | #define CONFIG_NR_DRAM_BANKS 8 |
8c5224c9 | 28 | #define CONFIG_X86_MRC_ADDR 0xfffa0000 |
65dd74a6 | 29 | #define CONFIG_CACHE_MRC_SIZE_KB 512 |
8ef07571 | 30 | |
41702bac | 31 | #define CONFIG_X86_SERIAL |
8ef07571 SG |
32 | |
33 | #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ | |
34 | PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ | |
35 | {PCI_VENDOR_ID_INTEL, \ | |
36 | PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ | |
37 | {PCI_VENDOR_ID_INTEL, \ | |
38 | PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ | |
39 | {PCI_VENDOR_ID_INTEL, \ | |
40 | PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} | |
41 | ||
63faf250 | 42 | #define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin |
62d0c5e1 SG |
43 | #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 |
44 | #define CONFIG_VIDEO_X86 | |
8ef07571 | 45 | |
6e5b12b6 SG |
46 | #define CONFIG_PCI_MEM_BUS 0xe0000000 |
47 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
48 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
49 | ||
50 | #define CONFIG_PCI_PREF_BUS 0xd0000000 | |
51 | #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS | |
52 | #define CONFIG_PCI_PREF_SIZE 0x10000000 | |
53 | ||
54 | #define CONFIG_PCI_IO_BUS 0x1000 | |
55 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
56 | #define CONFIG_PCI_IO_SIZE 0xefff | |
57 | ||
b6b4a0ec SG |
58 | #define CONFIG_SYS_EARLY_PCI_INIT |
59 | #define CONFIG_PCI_PNP | |
60 | ||
a6fa83f0 SG |
61 | #define CONFIG_BIOSEMU |
62 | #define VIDEO_IO_OFFSET 0 | |
63 | #define CONFIG_X86EMU_RAW_IO | |
64 | ||
22e131ca SG |
65 | #define CONFIG_CROS_EC |
66 | #define CONFIG_CROS_EC_LPC | |
67 | #define CONFIG_CMD_CROS_EC | |
68 | #define CONFIG_ARCH_EARLY_INIT_R | |
69 | ||
8ef07571 SG |
70 | #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ |
71 | "stdout=vga,serial\0" \ | |
72 | "stderr=vga,serial\0" | |
73 | ||
74 | #endif /* __CONFIG_H */ |