[people/ms/u-boot.git] / include / configs / cm5200.h

/*
 * (C) Copyright 2003-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_CM5200		1	/* ... on CM5200 platform */

#define	CONFIG_SYS_TEXT_BASE	0xfc000000

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Supported commands
 */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
#define CONFIG_MISC_INIT_R	1
#define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */

/*
 * POST support
 */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
/* List of I2C addresses to be verified by POST */
#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
					 CONFIG_SYS_I2C_IO,	\
					 CONFIG_SYS_I2C_EEPROM}

/* display image timestamps */
#define CONFIG_TIMESTAMP	1

/*
 * Autobooting
 */
#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
	"echo"
#undef CONFIG_BOOTARGS

/*
 * Default environment settings
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"netmask=255.255.0.0\0"						\
	"ipaddr=192.168.160.33\0"					\
	"serverip=192.168.1.1\0"					\
	"gatewayip=192.168.1.1\0"					\
	"console=ttyPSC0\0"						\
	"u-boot_addr=100000\0"						\
	"kernel_addr=200000\0"						\
	"kernel_addr_flash=fc0c0000\0"					\
	"fdt_addr=400000\0"						\
	"fdt_addr_flash=fc0a0000\0"					\
	"ramdisk_addr=500000\0"						\
	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
	"u-boot=/tftpboot/cm5200/u-boot.bin\0"				\
	"bootfile_fdt=/tftpboot/cm5200/uImage\0"			\
	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0"			\
	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
	"update=prot off fc000000 +${filesize}; "			\
		"era fc000000 +${filesize}; "				\
		"cp.b ${u-boot_addr} fc000000 ${filesize}; "		\
		"prot on fc000000 +${filesize}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"		\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0"		\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=${console},${baudrate}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
		"${netmask}:${hostname}:${netdev}:off panic=1\0"	\
	"flash_flash=run flashargs addinit addip addcons;"		\
		"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"	\
	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "		\
		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "	\
		"addcons; bootm ${kernel_addr} - ${fdt_addr}\0"		\
	""
#define CONFIG_BOOTCOMMAND	"run flash_flash"

/*
 * Low level configuration
 */

/*
 * Clock configuration
 */
#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_LOWBOOT		1

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_BOARD_TYPES	1	/* we use board_type */

#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_BASE		0xfc000000
/* we need these despite using CFI */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#undef CONFIG_SYS_LOWBOOT
#endif

/*
 * Chip selects configuration
 */
/* Boot Chipselect */
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
/* use board_early_init_r to enable flash write in CS_BOOT */
#define CONFIG_BOARD_EARLY_INIT_R

/* Flash memory addressing */
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* No burst, dead cycle = 1 for CS0 (Flash) */
#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x00000001

/*
 * SDRAM configuration
 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
 */
#define SDRAM_MODE	0x00CD0000	/* CASL 3, burst length 8 */
#define SDRAM_CONTROL	0x514F0000
#define SDRAM_CONFIG1	0xE2333900
#define SDRAM_CONFIG2	0x8EE70000

/*
 * MTD configuration
 */
#define CONFIG_CMD_MTDPARTS	1
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=cm5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
					"384k(uboot),128k(env),"	\
					"128k(redund_env),128k(dtb),"	\
					"2m(kernel),27904k(rootfs),"	\
					"-(config)"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_IO		0x38	/* PCA9554AD I2C I/O port address */
#define CONFIG_SYS_I2C_EEPROM		0x53	/* I2C EEPROM device address */

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * USB configuration
 */
#define CONFIG_USB_OHCI		1
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000
/* Partitions (for USB) */

/*
 * Invoke our last_stage_init function - needed by fwupdate
 */
#define CONFIG_LAST_STAGE_INIT	1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Configuration of redundant environment */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Pin multiplexing configuration
 */

/*
 * CS1/GPIO_WKUP_6: GPIO (default)
 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
 * IRDA/PSC6: UART
 * Ether: Ethernet 100Mbit with MD
 * PCI_DIS: PCI controller disabled
 * USB: USB
 * PSC3: SPI with UART3
 * PSC2: UART
 * PSC1: UART
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Flat Device Tree support
 */
#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

#endif /* __CONFIG_H */
Commit	Line	Data
fa1df308 BS	1	/*
	2	* (C) Copyright 2003-2007
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
fa1df308 BS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
b2a6dfe4	14	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
86b116b1	15	#define CONFIG_CM5200 1 /* ... on CM5200 platform */
fa1df308	16
2ae18241 WD	17	#define CONFIG_SYS_TEXT_BASE 0xfc000000
2ae18241 WD	18
31d82672 BB	19	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	20
fa1df308 BS	21	/*
	22	* Supported commands
	23	*/
afaac86f WD	24	#define CONFIG_CMD_BSP
afaac86f WD	25	#define CONFIG_CMD_DATE
afaac86f	26	#define CONFIG_CMD_DIAG
afaac86f	27	#define CONFIG_CMD_JFFS2
afaac86f	28	#define CONFIG_CMD_REGINFO
fa1df308 BS	29
	30	/*
	31	* Serial console configuration
	32	*/
	33	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
6d0f6bcf	34	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
fa1df308	35
fa1df308 BS	36	/*
	37	* Ethernet configuration
	38	*/
	39	#define CONFIG_MPC5xxx_FEC 1
86321fc1	40	#define CONFIG_MPC5xxx_FEC_MII100
fa1df308 BS	41	#define CONFIG_PHY_ADDR 0x00
fa1df308 BS	42	#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
6d0f6bcf	43	/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
fa1df308 BS	44	#define CONFIG_MISC_INIT_R 1
	45	#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
	46
fa1df308 BS	47	/*
	48	* POST support
	49	*/
6d0f6bcf	50	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| CONFIG_SYS_POST_CPU \| CONFIG_SYS_POST_I2C)
fa1df308 BS	51	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
fa1df308 BS	52	/* List of I2C addresses to be verified by POST */
60aaaa07 PT	53	#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
	54	CONFIG_SYS_I2C_IO, \
	55	CONFIG_SYS_I2C_EEPROM}
fa1df308	56
fa1df308 BS	57	/* display image timestamps */
	58	#define CONFIG_TIMESTAMP 1
	59
fa1df308 BS	60	/*
	61	* Autobooting
	62	*/
fa1df308 BS	63	#define CONFIG_PREBOOT "echo;" \
	64	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
	65	"echo"
	66	#undef CONFIG_BOOTARGS
	67
	68	/*
	69	* Default environment settings
	70	*/
	71	#define CONFIG_EXTRA_ENV_SETTINGS \
	72	"netdev=eth0\0" \
fa1df308 BS	73	"netmask=255.255.0.0\0" \
	74	"ipaddr=192.168.160.33\0" \
	75	"serverip=192.168.1.1\0" \
	76	"gatewayip=192.168.1.1\0" \
	77	"console=ttyPSC0\0" \
	78	"u-boot_addr=100000\0" \
	79	"kernel_addr=200000\0" \
	80	"kernel_addr_flash=fc0c0000\0" \
	81	"fdt_addr=400000\0" \
	82	"fdt_addr_flash=fc0a0000\0" \
	83	"ramdisk_addr=500000\0" \
	84	"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
86b116b1 BS	85	"u-boot=/tftpboot/cm5200/u-boot.bin\0" \
	86	"bootfile_fdt=/tftpboot/cm5200/uImage\0" \
	87	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
fa1df308	88	"load=tftp ${u-boot_addr} ${u-boot}\0" \
86b116b1 BS	89	"update=prot off fc000000 +${filesize}; " \
86b116b1 BS	90	"era fc000000 +${filesize}; " \
fa1df308	91	"cp.b ${u-boot_addr} fc000000 ${filesize}; " \
86b116b1	92	"prot on fc000000 +${filesize}\0" \
fa1df308 BS	93	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	94	"nfsroot=${serverip}:${rootpath}\0" \
	95	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
	96	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	97	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
	98	"addcons=setenv bootargs ${bootargs} " \
	99	"console=${console},${baudrate}\0" \
	100	"addip=setenv bootargs ${bootargs} " \
	101	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	102	"${netmask}:${hostname}:${netdev}:off panic=1\0" \
	103	"flash_flash=run flashargs addinit addip addcons;" \
	104	"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
	105	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
	106	"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
	107	"addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
	108	""
	109	#define CONFIG_BOOTCOMMAND "run flash_flash"
	110
fa1df308 BS	111	/*
	112	* Low level configuration
	113	*/
	114
fa1df308 BS	115	/*
	116	* Clock configuration
	117	*/
6d0f6bcf JCPV	118	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
6d0f6bcf JCPV	119	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
fa1df308	120
fa1df308 BS	121	/*
	122	* Memory map
	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_MBAR 0xF0000000
	125	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	126	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
fa1df308	127
6d0f6bcf	128	#define CONFIG_SYS_LOWBOOT 1
fa1df308 BS	129
fa1df308 BS	130	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	131	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
fa1df308 BS	132	#ifdef CONFIG_POST
fa1df308 BS	133	/* preserve space for the post_word at end of on-chip SRAM */
553f0982	134	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
fa1df308	135	#else
553f0982	136	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
fa1df308 BS	137	#endif
fa1df308 BS	138
25ddd1fb	139	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
86b116b1 BS	140	#define CONFIG_BOARD_TYPES 1 /* we use board_type */
86b116b1 BS	141
6d0f6bcf	142	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
fa1df308	143
14d0a02a	144	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	145	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
	146	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
	147	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
fa1df308	148
86b116b1 BS	149	/*
	150	* Flash configuration
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	153	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	154	#define CONFIG_SYS_FLASH_BASE 0xfc000000
86b116b1	155	/* we need these despite using CFI */
6d0f6bcf JCPV	156	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	157	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
	158	#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
86b116b1	159
6d0f6bcf JCPV	160	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	161	#define CONFIG_SYS_RAMBOOT 1
	162	#undef CONFIG_SYS_LOWBOOT
fa1df308 BS	163	#endif
fa1df308 BS	164
fa1df308 BS	165	/*
	166	* Chip selects configuration
	167	*/
	168	/* Boot Chipselect */
6d0f6bcf JCPV	169	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	170	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	171	#define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
fa1df308 BS	172	/* use board_early_init_r to enable flash write in CS_BOOT */
	173	#define CONFIG_BOARD_EARLY_INIT_R
	174
	175	/* Flash memory addressing */
6d0f6bcf JCPV	176	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	177	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
fa1df308 BS	178
fa1df308 BS	179	/* No burst, dead cycle = 1 for CS0 (Flash) */
6d0f6bcf JCPV	180	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	181	#define CONFIG_SYS_CS_DEADCYCLE 0x00000001
fa1df308	182
fa1df308 BS	183	/*
	184	* SDRAM configuration
	185	* settings for k4s561632E-xx75, assuming XLB = 132 MHz
	186	*/
	187	#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
	188	#define SDRAM_CONTROL 0x514F0000
	189	#define SDRAM_CONFIG1 0xE2333900
	190	#define SDRAM_CONFIG2 0x8EE70000
	191
fa1df308 BS	192	/*
	193	* MTD configuration
	194	*/
68d7d651	195	#define CONFIG_CMD_MTDPARTS 1
942556a9 SR	196	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	197	#define CONFIG_FLASH_CFI_MTD
86b116b1 BS	198	#define MTDIDS_DEFAULT "nor0=cm5200-0"
86b116b1 BS	199	#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
fa1df308 BS	200	"384k(uboot),128k(env)," \
	201	"128k(redund_env),128k(dtb)," \
	202	"2m(kernel),27904k(rootfs)," \
	203	"-(config)"
	204
fa1df308 BS	205	/*
	206	* I2C configuration
	207	*/
	208	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	209	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
	210	#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
	211	#define CONFIG_SYS_I2C_SLAVE 0x0
	212	#define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
	213	#define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
fa1df308	214
fa1df308 BS	215	/*
	216	* RTC configuration
	217	*/
	218	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	219
fa1df308 BS	220	/*
	221	* USB configuration
	222	*/
	223	#define CONFIG_USB_OHCI 1
fa1df308 BS	224	#define CONFIG_USB_CLOCK 0x0001BBBB
	225	#define CONFIG_USB_CONFIG 0x00001000
	226	/* Partitions (for USB) */
fa1df308 BS	227
	228	/*
	229	* Invoke our last_stage_init function - needed by fwupdate
	230	*/
	231	#define CONFIG_LAST_STAGE_INIT 1
	232
	233	/*
	234	* Environment settings
	235	*/
5a1aceb0	236	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	237	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	238	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	239	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
fa1df308	240	/* Configuration of redundant environment */
0e8d1586 JCPV	241	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	242	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
fa1df308	243
fa1df308 BS	244	/*
	245	* Pin multiplexing configuration
	246	*/
	247
	248	/*
	249	* CS1/GPIO_WKUP_6: GPIO (default)
	250	* ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
	251	* IRDA/PSC6: UART
	252	* Ether: Ethernet 100Mbit with MD
	253	* PCI_DIS: PCI controller disabled
	254	* USB: USB
	255	* PSC3: SPI with UART3
	256	* PSC2: UART
	257	* PSC1: UART
	258	*/
6d0f6bcf	259	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
fa1df308	260
fa1df308 BS	261	/*
	262	* Miscellaneous configurable options
	263	*/
6d0f6bcf	264	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	265	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	266	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	267	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	268	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
fa1df308	269
6d0f6bcf JCPV	270	#define CONFIG_SYS_ALT_MEMTEST 1
	271	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	272	#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
fa1df308	273
6d0f6bcf	274	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
fa1df308	275
fa1df308 BS	276	/*
	277	* Various low-level settings
	278	*/
6d0f6bcf JCPV	279	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	280	#define CONFIG_SYS_HID0_FINAL HID0_ICE
fa1df308	281
6d0f6bcf	282	#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
fa1df308	283
fa1df308 BS	284	/*
	285	* Cache Configuration
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
afaac86f	288	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	289	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
fa1df308 BS	290	#endif
fa1df308 BS	291
fa1df308 BS	292	/*
	293	* Flat Device Tree support
	294	*/
fa1df308 BS	295	#define OF_CPU "PowerPC,5200@0"
	296	#define OF_SOC "soc5200@f0000000"
	297	#define OF_TBCLK (bd->bi_busfreq / 4)
	298	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	299
	300	#endif /* __CONFIG_H */