]>
Commit | Line | Data |
---|---|---|
fa1df308 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fa1df308 BS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
001475a0 | 11 | |
001475a0 DB |
12 | #define CONFIG_DISPLAY_BOARDINFO |
13 | ||
14 | ||
fa1df308 BS |
15 | /* |
16 | * High Level Configuration Options | |
17 | */ | |
b2a6dfe4 | 18 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
86b116b1 | 19 | #define CONFIG_CM5200 1 /* ... on CM5200 platform */ |
fa1df308 | 20 | |
2ae18241 WD |
21 | #define CONFIG_SYS_TEXT_BASE 0xfc000000 |
22 | ||
31d82672 BB |
23 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
24 | ||
fa1df308 BS |
25 | /* |
26 | * Supported commands | |
27 | */ | |
afaac86f WD |
28 | #define CONFIG_CMD_ASKENV |
29 | #define CONFIG_CMD_BSP | |
30 | #define CONFIG_CMD_DATE | |
31 | #define CONFIG_CMD_DHCP | |
32 | #define CONFIG_CMD_DIAG | |
33 | #define CONFIG_CMD_FAT | |
34 | #define CONFIG_CMD_I2C | |
35 | #define CONFIG_CMD_JFFS2 | |
36 | #define CONFIG_CMD_MII | |
afaac86f WD |
37 | #define CONFIG_CMD_PING |
38 | #define CONFIG_CMD_REGINFO | |
39 | #define CONFIG_CMD_SNTP | |
40 | #define CONFIG_CMD_USB | |
fa1df308 BS |
41 | |
42 | /* | |
43 | * Serial console configuration | |
44 | */ | |
45 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
46 | #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
86b116b1 | 48 | #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ |
fa1df308 | 49 | |
fa1df308 BS |
50 | /* |
51 | * Ethernet configuration | |
52 | */ | |
53 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 54 | #define CONFIG_MPC5xxx_FEC_MII100 |
fa1df308 BS |
55 | #define CONFIG_PHY_ADDR 0x00 |
56 | #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ | |
6d0f6bcf | 57 | /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ |
fa1df308 BS |
58 | #define CONFIG_MISC_INIT_R 1 |
59 | #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ | |
60 | ||
fa1df308 BS |
61 | /* |
62 | * POST support | |
63 | */ | |
6d0f6bcf | 64 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C) |
fa1df308 BS |
65 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
66 | /* List of I2C addresses to be verified by POST */ | |
60aaaa07 PT |
67 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \ |
68 | CONFIG_SYS_I2C_IO, \ | |
69 | CONFIG_SYS_I2C_EEPROM} | |
fa1df308 | 70 | |
fa1df308 BS |
71 | /* display image timestamps */ |
72 | #define CONFIG_TIMESTAMP 1 | |
73 | ||
fa1df308 BS |
74 | /* |
75 | * Autobooting | |
76 | */ | |
77 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
78 | #define CONFIG_PREBOOT "echo;" \ | |
79 | "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ | |
80 | "echo" | |
81 | #undef CONFIG_BOOTARGS | |
82 | ||
83 | /* | |
84 | * Default environment settings | |
85 | */ | |
86 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
87 | "netdev=eth0\0" \ | |
fa1df308 BS |
88 | "netmask=255.255.0.0\0" \ |
89 | "ipaddr=192.168.160.33\0" \ | |
90 | "serverip=192.168.1.1\0" \ | |
91 | "gatewayip=192.168.1.1\0" \ | |
92 | "console=ttyPSC0\0" \ | |
93 | "u-boot_addr=100000\0" \ | |
94 | "kernel_addr=200000\0" \ | |
95 | "kernel_addr_flash=fc0c0000\0" \ | |
96 | "fdt_addr=400000\0" \ | |
97 | "fdt_addr_flash=fc0a0000\0" \ | |
98 | "ramdisk_addr=500000\0" \ | |
99 | "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ | |
86b116b1 BS |
100 | "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ |
101 | "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ | |
102 | "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ | |
fa1df308 | 103 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
86b116b1 BS |
104 | "update=prot off fc000000 +${filesize}; " \ |
105 | "era fc000000 +${filesize}; " \ | |
fa1df308 | 106 | "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ |
86b116b1 | 107 | "prot on fc000000 +${filesize}\0" \ |
fa1df308 BS |
108 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
109 | "nfsroot=${serverip}:${rootpath}\0" \ | |
110 | "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ | |
111 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
112 | "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ | |
113 | "addcons=setenv bootargs ${bootargs} " \ | |
114 | "console=${console},${baudrate}\0" \ | |
115 | "addip=setenv bootargs ${bootargs} " \ | |
116 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
117 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
118 | "flash_flash=run flashargs addinit addip addcons;" \ | |
119 | "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ | |
120 | "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ | |
121 | "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ | |
122 | "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
123 | "" | |
124 | #define CONFIG_BOOTCOMMAND "run flash_flash" | |
125 | ||
fa1df308 BS |
126 | /* |
127 | * Low level configuration | |
128 | */ | |
129 | ||
fa1df308 BS |
130 | /* |
131 | * Clock configuration | |
132 | */ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ |
134 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ | |
fa1df308 | 135 | |
fa1df308 BS |
136 | /* |
137 | * Memory map | |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MBAR 0xF0000000 |
140 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
141 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
fa1df308 | 142 | |
6d0f6bcf | 143 | #define CONFIG_SYS_LOWBOOT 1 |
fa1df308 BS |
144 | |
145 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 146 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
fa1df308 BS |
147 | #ifdef CONFIG_POST |
148 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 149 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
fa1df308 | 150 | #else |
553f0982 | 151 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
fa1df308 BS |
152 | #endif |
153 | ||
25ddd1fb | 154 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
86b116b1 BS |
155 | #define CONFIG_BOARD_TYPES 1 /* we use board_type */ |
156 | ||
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fa1df308 | 158 | |
14d0a02a | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ |
161 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ | |
162 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
fa1df308 | 163 | |
86b116b1 BS |
164 | /* |
165 | * Flash configuration | |
166 | */ | |
6d0f6bcf | 167 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 168 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 169 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
86b116b1 | 170 | /* we need these despite using CFI */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
172 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ | |
173 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ | |
86b116b1 BS |
174 | |
175 | ||
6d0f6bcf JCPV |
176 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
177 | #define CONFIG_SYS_RAMBOOT 1 | |
178 | #undef CONFIG_SYS_LOWBOOT | |
fa1df308 BS |
179 | #endif |
180 | ||
181 | ||
182 | /* | |
183 | * Chip selects configuration | |
184 | */ | |
185 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
187 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
188 | #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ | |
fa1df308 BS |
189 | /* use board_early_init_r to enable flash write in CS_BOOT */ |
190 | #define CONFIG_BOARD_EARLY_INIT_R | |
191 | ||
192 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
194 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
fa1df308 BS |
195 | |
196 | /* No burst, dead cycle = 1 for CS0 (Flash) */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_CS_BURST 0x00000000 |
198 | #define CONFIG_SYS_CS_DEADCYCLE 0x00000001 | |
fa1df308 | 199 | |
fa1df308 BS |
200 | /* |
201 | * SDRAM configuration | |
202 | * settings for k4s561632E-xx75, assuming XLB = 132 MHz | |
203 | */ | |
204 | #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ | |
205 | #define SDRAM_CONTROL 0x514F0000 | |
206 | #define SDRAM_CONFIG1 0xE2333900 | |
207 | #define SDRAM_CONFIG2 0x8EE70000 | |
208 | ||
fa1df308 BS |
209 | /* |
210 | * MTD configuration | |
211 | */ | |
68d7d651 | 212 | #define CONFIG_CMD_MTDPARTS 1 |
942556a9 SR |
213 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
214 | #define CONFIG_FLASH_CFI_MTD | |
86b116b1 BS |
215 | #define MTDIDS_DEFAULT "nor0=cm5200-0" |
216 | #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ | |
fa1df308 BS |
217 | "384k(uboot),128k(env)," \ |
218 | "128k(redund_env),128k(dtb)," \ | |
219 | "2m(kernel),27904k(rootfs)," \ | |
220 | "-(config)" | |
221 | ||
fa1df308 BS |
222 | /* |
223 | * I2C configuration | |
224 | */ | |
225 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ |
227 | #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */ | |
228 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
229 | #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ | |
230 | #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */ | |
fa1df308 | 231 | |
fa1df308 BS |
232 | /* |
233 | * RTC configuration | |
234 | */ | |
235 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
236 | ||
fa1df308 BS |
237 | /* |
238 | * USB configuration | |
239 | */ | |
240 | #define CONFIG_USB_OHCI 1 | |
241 | #define CONFIG_USB_STORAGE 1 | |
242 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
243 | #define CONFIG_USB_CONFIG 0x00001000 | |
244 | /* Partitions (for USB) */ | |
245 | #define CONFIG_MAC_PARTITION 1 | |
246 | #define CONFIG_DOS_PARTITION 1 | |
247 | #define CONFIG_ISO_PARTITION 1 | |
248 | ||
249 | /* | |
250 | * Invoke our last_stage_init function - needed by fwupdate | |
251 | */ | |
252 | #define CONFIG_LAST_STAGE_INIT 1 | |
253 | ||
254 | /* | |
255 | * Environment settings | |
256 | */ | |
5a1aceb0 | 257 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
258 | #define CONFIG_ENV_SIZE 0x10000 |
259 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
6d0f6bcf | 260 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
fa1df308 | 261 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
262 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
263 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
fa1df308 | 264 | |
fa1df308 BS |
265 | /* |
266 | * Pin multiplexing configuration | |
267 | */ | |
268 | ||
269 | /* | |
270 | * CS1/GPIO_WKUP_6: GPIO (default) | |
271 | * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 | |
272 | * IRDA/PSC6: UART | |
273 | * Ether: Ethernet 100Mbit with MD | |
274 | * PCI_DIS: PCI controller disabled | |
275 | * USB: USB | |
276 | * PSC3: SPI with UART3 | |
277 | * PSC2: UART | |
278 | * PSC1: UART | |
279 | */ | |
6d0f6bcf | 280 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44 |
fa1df308 | 281 | |
fa1df308 BS |
282 | /* |
283 | * Miscellaneous configurable options | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
287 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
288 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
289 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
fa1df308 | 290 | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_ALT_MEMTEST 1 |
292 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
293 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ | |
fa1df308 BS |
294 | |
295 | #define CONFIG_LOOPW 1 | |
296 | ||
6d0f6bcf | 297 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
fa1df308 | 298 | |
fa1df308 BS |
299 | /* |
300 | * Various low-level settings | |
301 | */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
303 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
fa1df308 | 304 | |
6d0f6bcf | 305 | #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */ |
fa1df308 | 306 | |
fa1df308 BS |
307 | /* |
308 | * Cache Configuration | |
309 | */ | |
6d0f6bcf | 310 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
afaac86f | 311 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 312 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fa1df308 BS |
313 | #endif |
314 | ||
fa1df308 BS |
315 | /* |
316 | * Flat Device Tree support | |
317 | */ | |
fa1df308 BS |
318 | #define OF_CPU "PowerPC,5200@0" |
319 | #define OF_SOC "soc5200@f0000000" | |
320 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
321 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
322 | ||
323 | #endif /* __CONFIG_H */ |