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1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | */ | |
30 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
31 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
86b116b1 | 32 | #define CONFIG_CM5200 1 /* ... on CM5200 platform */ |
fa1df308 | 33 | |
2ae18241 WD |
34 | #define CONFIG_SYS_TEXT_BASE 0xfc000000 |
35 | ||
31d82672 BB |
36 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
37 | ||
fa1df308 BS |
38 | /* |
39 | * Supported commands | |
40 | */ | |
afaac86f WD |
41 | #include <config_cmd_default.h> |
42 | ||
43 | #define CONFIG_CMD_ASKENV | |
44 | #define CONFIG_CMD_BSP | |
45 | #define CONFIG_CMD_DATE | |
46 | #define CONFIG_CMD_DHCP | |
47 | #define CONFIG_CMD_DIAG | |
48 | #define CONFIG_CMD_FAT | |
49 | #define CONFIG_CMD_I2C | |
50 | #define CONFIG_CMD_JFFS2 | |
51 | #define CONFIG_CMD_MII | |
52 | #define CONFIG_CMD_NFS | |
53 | #define CONFIG_CMD_PING | |
54 | #define CONFIG_CMD_REGINFO | |
55 | #define CONFIG_CMD_SNTP | |
56 | #define CONFIG_CMD_USB | |
fa1df308 BS |
57 | |
58 | /* | |
59 | * Serial console configuration | |
60 | */ | |
61 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
62 | #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ | |
6d0f6bcf | 63 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
86b116b1 | 64 | #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ |
fa1df308 | 65 | |
fa1df308 BS |
66 | /* |
67 | * Ethernet configuration | |
68 | */ | |
69 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 70 | #define CONFIG_MPC5xxx_FEC_MII100 |
fa1df308 BS |
71 | #define CONFIG_PHY_ADDR 0x00 |
72 | #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ | |
6d0f6bcf | 73 | /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ |
fa1df308 BS |
74 | #define CONFIG_MISC_INIT_R 1 |
75 | #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ | |
76 | ||
fa1df308 BS |
77 | /* |
78 | * POST support | |
79 | */ | |
6d0f6bcf | 80 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C) |
fa1df308 BS |
81 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
82 | /* List of I2C addresses to be verified by POST */ | |
6d0f6bcf | 83 | #define I2C_ADDR_LIST { CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM } |
fa1df308 | 84 | |
fa1df308 BS |
85 | /* display image timestamps */ |
86 | #define CONFIG_TIMESTAMP 1 | |
87 | ||
fa1df308 BS |
88 | /* |
89 | * Autobooting | |
90 | */ | |
91 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
92 | #define CONFIG_PREBOOT "echo;" \ | |
93 | "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ | |
94 | "echo" | |
95 | #undef CONFIG_BOOTARGS | |
96 | ||
97 | /* | |
98 | * Default environment settings | |
99 | */ | |
100 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
101 | "netdev=eth0\0" \ | |
fa1df308 BS |
102 | "netmask=255.255.0.0\0" \ |
103 | "ipaddr=192.168.160.33\0" \ | |
104 | "serverip=192.168.1.1\0" \ | |
105 | "gatewayip=192.168.1.1\0" \ | |
106 | "console=ttyPSC0\0" \ | |
107 | "u-boot_addr=100000\0" \ | |
108 | "kernel_addr=200000\0" \ | |
109 | "kernel_addr_flash=fc0c0000\0" \ | |
110 | "fdt_addr=400000\0" \ | |
111 | "fdt_addr_flash=fc0a0000\0" \ | |
112 | "ramdisk_addr=500000\0" \ | |
113 | "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ | |
86b116b1 BS |
114 | "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ |
115 | "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ | |
116 | "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ | |
fa1df308 | 117 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
86b116b1 BS |
118 | "update=prot off fc000000 +${filesize}; " \ |
119 | "era fc000000 +${filesize}; " \ | |
fa1df308 | 120 | "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ |
86b116b1 | 121 | "prot on fc000000 +${filesize}\0" \ |
fa1df308 BS |
122 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
123 | "nfsroot=${serverip}:${rootpath}\0" \ | |
124 | "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ | |
125 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
126 | "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ | |
127 | "addcons=setenv bootargs ${bootargs} " \ | |
128 | "console=${console},${baudrate}\0" \ | |
129 | "addip=setenv bootargs ${bootargs} " \ | |
130 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
131 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
132 | "flash_flash=run flashargs addinit addip addcons;" \ | |
133 | "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ | |
134 | "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ | |
135 | "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ | |
136 | "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
137 | "" | |
138 | #define CONFIG_BOOTCOMMAND "run flash_flash" | |
139 | ||
fa1df308 BS |
140 | /* |
141 | * Low level configuration | |
142 | */ | |
143 | ||
fa1df308 BS |
144 | /* |
145 | * Clock configuration | |
146 | */ | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ |
148 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ | |
fa1df308 | 149 | |
fa1df308 BS |
150 | /* |
151 | * Memory map | |
152 | */ | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_MBAR 0xF0000000 |
154 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
155 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
fa1df308 | 156 | |
6d0f6bcf | 157 | #define CONFIG_SYS_LOWBOOT 1 |
fa1df308 BS |
158 | |
159 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 160 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
fa1df308 BS |
161 | #ifdef CONFIG_POST |
162 | /* preserve space for the post_word at end of on-chip SRAM */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE |
fa1df308 | 164 | #else |
6d0f6bcf | 165 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE |
fa1df308 BS |
166 | #endif |
167 | ||
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */ |
169 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
86b116b1 BS |
170 | #define CONFIG_BOARD_TYPES 1 /* we use board_type */ |
171 | ||
6d0f6bcf | 172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fa1df308 | 173 | |
14d0a02a | 174 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ |
176 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ | |
177 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
fa1df308 | 178 | |
86b116b1 BS |
179 | /* |
180 | * Flash configuration | |
181 | */ | |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 183 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 184 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
86b116b1 | 185 | /* we need these despite using CFI */ |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
187 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ | |
188 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ | |
86b116b1 BS |
189 | |
190 | ||
6d0f6bcf JCPV |
191 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
192 | #define CONFIG_SYS_RAMBOOT 1 | |
193 | #undef CONFIG_SYS_LOWBOOT | |
fa1df308 BS |
194 | #endif |
195 | ||
196 | ||
197 | /* | |
198 | * Chip selects configuration | |
199 | */ | |
200 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
202 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
203 | #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ | |
fa1df308 BS |
204 | /* use board_early_init_r to enable flash write in CS_BOOT */ |
205 | #define CONFIG_BOARD_EARLY_INIT_R | |
206 | ||
207 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
209 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
fa1df308 BS |
210 | |
211 | /* No burst, dead cycle = 1 for CS0 (Flash) */ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_CS_BURST 0x00000000 |
213 | #define CONFIG_SYS_CS_DEADCYCLE 0x00000001 | |
fa1df308 | 214 | |
fa1df308 BS |
215 | /* |
216 | * SDRAM configuration | |
217 | * settings for k4s561632E-xx75, assuming XLB = 132 MHz | |
218 | */ | |
219 | #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ | |
220 | #define SDRAM_CONTROL 0x514F0000 | |
221 | #define SDRAM_CONFIG1 0xE2333900 | |
222 | #define SDRAM_CONFIG2 0x8EE70000 | |
223 | ||
fa1df308 BS |
224 | /* |
225 | * MTD configuration | |
226 | */ | |
68d7d651 | 227 | #define CONFIG_CMD_MTDPARTS 1 |
942556a9 SR |
228 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
229 | #define CONFIG_FLASH_CFI_MTD | |
86b116b1 BS |
230 | #define MTDIDS_DEFAULT "nor0=cm5200-0" |
231 | #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ | |
fa1df308 BS |
232 | "384k(uboot),128k(env)," \ |
233 | "128k(redund_env),128k(dtb)," \ | |
234 | "2m(kernel),27904k(rootfs)," \ | |
235 | "-(config)" | |
236 | ||
fa1df308 BS |
237 | /* |
238 | * I2C configuration | |
239 | */ | |
240 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ |
242 | #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */ | |
243 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
244 | #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ | |
245 | #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */ | |
fa1df308 | 246 | |
fa1df308 BS |
247 | /* |
248 | * RTC configuration | |
249 | */ | |
250 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
251 | ||
fa1df308 BS |
252 | /* |
253 | * USB configuration | |
254 | */ | |
255 | #define CONFIG_USB_OHCI 1 | |
256 | #define CONFIG_USB_STORAGE 1 | |
257 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
258 | #define CONFIG_USB_CONFIG 0x00001000 | |
259 | /* Partitions (for USB) */ | |
260 | #define CONFIG_MAC_PARTITION 1 | |
261 | #define CONFIG_DOS_PARTITION 1 | |
262 | #define CONFIG_ISO_PARTITION 1 | |
263 | ||
264 | /* | |
265 | * Invoke our last_stage_init function - needed by fwupdate | |
266 | */ | |
267 | #define CONFIG_LAST_STAGE_INIT 1 | |
268 | ||
269 | /* | |
270 | * Environment settings | |
271 | */ | |
5a1aceb0 | 272 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
273 | #define CONFIG_ENV_SIZE 0x10000 |
274 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
6d0f6bcf | 275 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
fa1df308 | 276 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
277 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
278 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
fa1df308 | 279 | |
fa1df308 BS |
280 | /* |
281 | * Pin multiplexing configuration | |
282 | */ | |
283 | ||
284 | /* | |
285 | * CS1/GPIO_WKUP_6: GPIO (default) | |
286 | * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 | |
287 | * IRDA/PSC6: UART | |
288 | * Ether: Ethernet 100Mbit with MD | |
289 | * PCI_DIS: PCI controller disabled | |
290 | * USB: USB | |
291 | * PSC3: SPI with UART3 | |
292 | * PSC2: UART | |
293 | * PSC1: UART | |
294 | */ | |
6d0f6bcf | 295 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44 |
fa1df308 | 296 | |
fa1df308 BS |
297 | /* |
298 | * Miscellaneous configurable options | |
299 | */ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
301 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
302 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
303 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
304 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
305 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
fa1df308 | 306 | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_ALT_MEMTEST 1 |
308 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
309 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ | |
fa1df308 BS |
310 | |
311 | #define CONFIG_LOOPW 1 | |
312 | ||
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
314 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
fa1df308 | 315 | |
fa1df308 BS |
316 | /* |
317 | * Various low-level settings | |
318 | */ | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
320 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
fa1df308 | 321 | |
6d0f6bcf | 322 | #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */ |
fa1df308 | 323 | |
fa1df308 BS |
324 | /* |
325 | * Cache Configuration | |
326 | */ | |
6d0f6bcf | 327 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
afaac86f | 328 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 329 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fa1df308 BS |
330 | #endif |
331 | ||
fa1df308 BS |
332 | /* |
333 | * Flat Device Tree support | |
334 | */ | |
86b116b1 | 335 | #define CONFIG_OF_LIBFDT 1 |
fa1df308 | 336 | #define CONFIG_OF_BOARD_SETUP 1 |
fa1df308 BS |
337 | #define OF_CPU "PowerPC,5200@0" |
338 | #define OF_SOC "soc5200@f0000000" | |
339 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
340 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
341 | ||
342 | #endif /* __CONFIG_H */ |