]>
Commit | Line | Data |
---|---|---|
fa1df308 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fa1df308 BS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
001475a0 DB |
11 | |
12 | #define CONFIG_SYS_GENERIC_BOARD | |
13 | #define CONFIG_DISPLAY_BOARDINFO | |
14 | ||
15 | ||
fa1df308 BS |
16 | /* |
17 | * High Level Configuration Options | |
18 | */ | |
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
86b116b1 | 20 | #define CONFIG_CM5200 1 /* ... on CM5200 platform */ |
fa1df308 | 21 | |
2ae18241 WD |
22 | #define CONFIG_SYS_TEXT_BASE 0xfc000000 |
23 | ||
31d82672 BB |
24 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
25 | ||
fa1df308 BS |
26 | /* |
27 | * Supported commands | |
28 | */ | |
afaac86f WD |
29 | #define CONFIG_CMD_ASKENV |
30 | #define CONFIG_CMD_BSP | |
31 | #define CONFIG_CMD_DATE | |
32 | #define CONFIG_CMD_DHCP | |
33 | #define CONFIG_CMD_DIAG | |
34 | #define CONFIG_CMD_FAT | |
35 | #define CONFIG_CMD_I2C | |
36 | #define CONFIG_CMD_JFFS2 | |
37 | #define CONFIG_CMD_MII | |
afaac86f WD |
38 | #define CONFIG_CMD_PING |
39 | #define CONFIG_CMD_REGINFO | |
40 | #define CONFIG_CMD_SNTP | |
41 | #define CONFIG_CMD_USB | |
fa1df308 BS |
42 | |
43 | /* | |
44 | * Serial console configuration | |
45 | */ | |
46 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
47 | #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ | |
6d0f6bcf | 48 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
86b116b1 | 49 | #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ |
fa1df308 | 50 | |
fa1df308 BS |
51 | /* |
52 | * Ethernet configuration | |
53 | */ | |
54 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 55 | #define CONFIG_MPC5xxx_FEC_MII100 |
fa1df308 BS |
56 | #define CONFIG_PHY_ADDR 0x00 |
57 | #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ | |
6d0f6bcf | 58 | /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ |
fa1df308 BS |
59 | #define CONFIG_MISC_INIT_R 1 |
60 | #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ | |
61 | ||
fa1df308 BS |
62 | /* |
63 | * POST support | |
64 | */ | |
6d0f6bcf | 65 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C) |
fa1df308 BS |
66 | #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) |
67 | /* List of I2C addresses to be verified by POST */ | |
60aaaa07 PT |
68 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \ |
69 | CONFIG_SYS_I2C_IO, \ | |
70 | CONFIG_SYS_I2C_EEPROM} | |
fa1df308 | 71 | |
fa1df308 BS |
72 | /* display image timestamps */ |
73 | #define CONFIG_TIMESTAMP 1 | |
74 | ||
fa1df308 BS |
75 | /* |
76 | * Autobooting | |
77 | */ | |
78 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
79 | #define CONFIG_PREBOOT "echo;" \ | |
80 | "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ | |
81 | "echo" | |
82 | #undef CONFIG_BOOTARGS | |
83 | ||
84 | /* | |
85 | * Default environment settings | |
86 | */ | |
87 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
88 | "netdev=eth0\0" \ | |
fa1df308 BS |
89 | "netmask=255.255.0.0\0" \ |
90 | "ipaddr=192.168.160.33\0" \ | |
91 | "serverip=192.168.1.1\0" \ | |
92 | "gatewayip=192.168.1.1\0" \ | |
93 | "console=ttyPSC0\0" \ | |
94 | "u-boot_addr=100000\0" \ | |
95 | "kernel_addr=200000\0" \ | |
96 | "kernel_addr_flash=fc0c0000\0" \ | |
97 | "fdt_addr=400000\0" \ | |
98 | "fdt_addr_flash=fc0a0000\0" \ | |
99 | "ramdisk_addr=500000\0" \ | |
100 | "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ | |
86b116b1 BS |
101 | "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ |
102 | "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ | |
103 | "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ | |
fa1df308 | 104 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
86b116b1 BS |
105 | "update=prot off fc000000 +${filesize}; " \ |
106 | "era fc000000 +${filesize}; " \ | |
fa1df308 | 107 | "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ |
86b116b1 | 108 | "prot on fc000000 +${filesize}\0" \ |
fa1df308 BS |
109 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
110 | "nfsroot=${serverip}:${rootpath}\0" \ | |
111 | "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ | |
112 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
113 | "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ | |
114 | "addcons=setenv bootargs ${bootargs} " \ | |
115 | "console=${console},${baudrate}\0" \ | |
116 | "addip=setenv bootargs ${bootargs} " \ | |
117 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
118 | "${netmask}:${hostname}:${netdev}:off panic=1\0" \ | |
119 | "flash_flash=run flashargs addinit addip addcons;" \ | |
120 | "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ | |
121 | "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ | |
122 | "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ | |
123 | "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
124 | "" | |
125 | #define CONFIG_BOOTCOMMAND "run flash_flash" | |
126 | ||
fa1df308 BS |
127 | /* |
128 | * Low level configuration | |
129 | */ | |
130 | ||
fa1df308 BS |
131 | /* |
132 | * Clock configuration | |
133 | */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ |
135 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ | |
fa1df308 | 136 | |
fa1df308 BS |
137 | /* |
138 | * Memory map | |
139 | */ | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_MBAR 0xF0000000 |
141 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
142 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
fa1df308 | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_LOWBOOT 1 |
fa1df308 BS |
145 | |
146 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 147 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
fa1df308 BS |
148 | #ifdef CONFIG_POST |
149 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 150 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
fa1df308 | 151 | #else |
553f0982 | 152 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
fa1df308 BS |
153 | #endif |
154 | ||
25ddd1fb | 155 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
86b116b1 BS |
156 | #define CONFIG_BOARD_TYPES 1 /* we use board_type */ |
157 | ||
6d0f6bcf | 158 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fa1df308 | 159 | |
14d0a02a | 160 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ |
162 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ | |
163 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
fa1df308 | 164 | |
86b116b1 BS |
165 | /* |
166 | * Flash configuration | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 169 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 170 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 |
86b116b1 | 171 | /* we need these despite using CFI */ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
173 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ | |
174 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ | |
86b116b1 BS |
175 | |
176 | ||
6d0f6bcf JCPV |
177 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
178 | #define CONFIG_SYS_RAMBOOT 1 | |
179 | #undef CONFIG_SYS_LOWBOOT | |
fa1df308 BS |
180 | #endif |
181 | ||
182 | ||
183 | /* | |
184 | * Chip selects configuration | |
185 | */ | |
186 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
188 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
189 | #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ | |
fa1df308 BS |
190 | /* use board_early_init_r to enable flash write in CS_BOOT */ |
191 | #define CONFIG_BOARD_EARLY_INIT_R | |
192 | ||
193 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
195 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
fa1df308 BS |
196 | |
197 | /* No burst, dead cycle = 1 for CS0 (Flash) */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_CS_BURST 0x00000000 |
199 | #define CONFIG_SYS_CS_DEADCYCLE 0x00000001 | |
fa1df308 | 200 | |
fa1df308 BS |
201 | /* |
202 | * SDRAM configuration | |
203 | * settings for k4s561632E-xx75, assuming XLB = 132 MHz | |
204 | */ | |
205 | #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ | |
206 | #define SDRAM_CONTROL 0x514F0000 | |
207 | #define SDRAM_CONFIG1 0xE2333900 | |
208 | #define SDRAM_CONFIG2 0x8EE70000 | |
209 | ||
fa1df308 BS |
210 | /* |
211 | * MTD configuration | |
212 | */ | |
68d7d651 | 213 | #define CONFIG_CMD_MTDPARTS 1 |
942556a9 SR |
214 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
215 | #define CONFIG_FLASH_CFI_MTD | |
86b116b1 BS |
216 | #define MTDIDS_DEFAULT "nor0=cm5200-0" |
217 | #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ | |
fa1df308 BS |
218 | "384k(uboot),128k(env)," \ |
219 | "128k(redund_env),128k(dtb)," \ | |
220 | "2m(kernel),27904k(rootfs)," \ | |
221 | "-(config)" | |
222 | ||
fa1df308 BS |
223 | /* |
224 | * I2C configuration | |
225 | */ | |
226 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */ |
228 | #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */ | |
229 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
230 | #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ | |
231 | #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */ | |
fa1df308 | 232 | |
fa1df308 BS |
233 | /* |
234 | * RTC configuration | |
235 | */ | |
236 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
237 | ||
fa1df308 BS |
238 | /* |
239 | * USB configuration | |
240 | */ | |
241 | #define CONFIG_USB_OHCI 1 | |
242 | #define CONFIG_USB_STORAGE 1 | |
243 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
244 | #define CONFIG_USB_CONFIG 0x00001000 | |
245 | /* Partitions (for USB) */ | |
246 | #define CONFIG_MAC_PARTITION 1 | |
247 | #define CONFIG_DOS_PARTITION 1 | |
248 | #define CONFIG_ISO_PARTITION 1 | |
249 | ||
250 | /* | |
251 | * Invoke our last_stage_init function - needed by fwupdate | |
252 | */ | |
253 | #define CONFIG_LAST_STAGE_INIT 1 | |
254 | ||
255 | /* | |
256 | * Environment settings | |
257 | */ | |
5a1aceb0 | 258 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
259 | #define CONFIG_ENV_SIZE 0x10000 |
260 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
6d0f6bcf | 261 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
fa1df308 | 262 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
263 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
264 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
fa1df308 | 265 | |
fa1df308 BS |
266 | /* |
267 | * Pin multiplexing configuration | |
268 | */ | |
269 | ||
270 | /* | |
271 | * CS1/GPIO_WKUP_6: GPIO (default) | |
272 | * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 | |
273 | * IRDA/PSC6: UART | |
274 | * Ether: Ethernet 100Mbit with MD | |
275 | * PCI_DIS: PCI controller disabled | |
276 | * USB: USB | |
277 | * PSC3: SPI with UART3 | |
278 | * PSC2: UART | |
279 | * PSC1: UART | |
280 | */ | |
6d0f6bcf | 281 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44 |
fa1df308 | 282 | |
fa1df308 BS |
283 | /* |
284 | * Miscellaneous configurable options | |
285 | */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
288 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
289 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
290 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
fa1df308 | 291 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_ALT_MEMTEST 1 |
293 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ | |
294 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ | |
fa1df308 BS |
295 | |
296 | #define CONFIG_LOOPW 1 | |
297 | ||
6d0f6bcf | 298 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
fa1df308 | 299 | |
fa1df308 BS |
300 | /* |
301 | * Various low-level settings | |
302 | */ | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
304 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
fa1df308 | 305 | |
6d0f6bcf | 306 | #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */ |
fa1df308 | 307 | |
fa1df308 BS |
308 | /* |
309 | * Cache Configuration | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
afaac86f | 312 | #ifdef CONFIG_CMD_KGDB |
6d0f6bcf | 313 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fa1df308 BS |
314 | #endif |
315 | ||
fa1df308 BS |
316 | /* |
317 | * Flat Device Tree support | |
318 | */ | |
86b116b1 | 319 | #define CONFIG_OF_LIBFDT 1 |
fa1df308 | 320 | #define CONFIG_OF_BOARD_SETUP 1 |
fa1df308 BS |
321 | #define OF_CPU "PowerPC,5200@0" |
322 | #define OF_SOC "soc5200@f0000000" | |
323 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
324 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
325 | ||
326 | #endif /* __CONFIG_H */ |