]>
Commit | Line | Data |
---|---|---|
2cbe571a | 1 | /* |
414eec35 | 2 | * 2004-2005 Gary Jennejohn <garyj@denx.de> |
2cbe571a | 3 | * |
9d5028c2 | 4 | * Configuration settings for the CMC PU2 board. |
2cbe571a WD |
5 | * |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
45ea3fca | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
2cbe571a WD |
17 | * GNU General Public License for more details. |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
2cbe571a | 28 | /* ARM asynchronous clock */ |
df3c7c8f | 29 | #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ |
101e8dfa | 30 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ |
2cbe571a WD |
31 | |
32 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | |
33 | ||
a85f9f21 WD |
34 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
35 | #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ | |
a85f9f21 WD |
36 | #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ |
37 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
38 | #define USE_920T_MMU 1 | |
39 | ||
2cbe571a WD |
40 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
41 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
42 | #define CONFIG_INITRD_TAG 1 | |
43 | ||
8aa1a2d1 | 44 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
6d0f6bcf | 45 | #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 |
ef2807c6 | 46 | /* flash */ |
d481c80d JCPV |
47 | #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 |
48 | #define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ | |
ef2807c6 WD |
49 | |
50 | /* clocks */ | |
d481c80d JCPV |
51 | #define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ |
52 | #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ | |
53 | #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ | |
ef2807c6 WD |
54 | |
55 | /* sdram */ | |
d481c80d JCPV |
56 | #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ |
57 | #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 | |
58 | #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 | |
59 | #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ | |
60 | #define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */ | |
61 | #define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ | |
62 | #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ | |
63 | #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ | |
64 | #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ | |
65 | #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ | |
66 | #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ | |
67 | #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ | |
68 | #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ | |
8052352f JS |
69 | #else |
70 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
8aa1a2d1 | 71 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
ef2807c6 | 72 | |
2cbe571a WD |
73 | /* |
74 | * Size of malloc() pool | |
75 | */ | |
6d0f6bcf JCPV |
76 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
77 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
2cbe571a | 78 | |
45ea3fca | 79 | #define CONFIG_BAUDRATE 9600 |
2cbe571a | 80 | |
2cbe571a WD |
81 | /* |
82 | * Hardware drivers | |
83 | */ | |
84 | ||
85 | /* define one of these to choose the DBGU, USART0 or USART1 as console */ | |
beebd851 | 86 | #define CONFIG_AT91RM9200_USART |
2cbe571a | 87 | #undef CONFIG_DBGU |
9d5028c2 WD |
88 | #define CONFIG_USART0 |
89 | #undef CONFIG_USART1 | |
2cbe571a WD |
90 | |
91 | #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ | |
92 | ||
93 | #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ | |
94 | ||
9d5028c2 | 95 | #define CONFIG_HARD_I2C |
2cbe571a WD |
96 | |
97 | #ifdef CONFIG_HARD_I2C | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_I2C_SPEED 0 /* not used */ |
99 | #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ | |
45ea3fca | 100 | #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_I2C_RTC_ADDR 0x32 |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
103 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
104 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW | |
37e4f24b JL |
105 | #else |
106 | #define CONFIG_TIMESTAMP | |
2cbe571a | 107 | #endif |
ed54e621 | 108 | /* still about 20 kB free with this defined */ |
6d0f6bcf | 109 | #define CONFIG_SYS_LONGHELP |
2cbe571a | 110 | |
1ac7e17e | 111 | #define CONFIG_BOOTDELAY 1 |
2cbe571a | 112 | |
37e4f24b | 113 | |
80ff4f99 JL |
114 | /* |
115 | * BOOTP options | |
116 | */ | |
117 | #define CONFIG_BOOTP_BOOTFILESIZE | |
118 | #define CONFIG_BOOTP_BOOTPATH | |
119 | #define CONFIG_BOOTP_GATEWAY | |
120 | #define CONFIG_BOOTP_HOSTNAME | |
121 | ||
122 | ||
37e4f24b JL |
123 | /* |
124 | * Command line configuration. | |
125 | */ | |
126 | #include <config_cmd_default.h> | |
127 | ||
128 | #define CONFIG_CMD_DHCP | |
129 | #define CONFIG_CMD_NFS | |
130 | #define CONFIG_CMD_SNTP | |
131 | ||
132 | #undef CONFIG_CMD_FPGA | |
133 | #undef CONFIG_CMD_MISC | |
134 | ||
135 | #if defined(CONFIG_HARD_I2C) | |
136 | #define CONFIG_CMD_DATE | |
137 | #define CONFIG_CMD_EEPROM | |
138 | #define CONFIG_CMD_I2C | |
2cbe571a WD |
139 | #endif |
140 | ||
37e4f24b | 141 | |
92b50ffe | 142 | #define CONFIG_MISC_INIT_R |
6d0f6bcf | 143 | #define CONFIG_SYS_LONGHELP |
2cbe571a | 144 | |
45ea3fca WD |
145 | #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ |
146 | #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ | |
2cbe571a | 147 | |
45ea3fca WD |
148 | #define CONFIG_NR_DRAM_BANKS 1 |
149 | #define PHYS_SDRAM 0x20000000 | |
2c5260f7 | 150 | #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ |
2cbe571a | 151 | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
153 | #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 | |
2cbe571a WD |
154 | |
155 | #define CONFIG_DRIVER_ETHER | |
156 | #define CONFIG_NET_RETRY_COUNT 20 | |
157 | #define CONFIG_AT91C_USE_RMII | |
158 | ||
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) |
160 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 | |
161 | #define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 | |
162 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ | |
163 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ | |
2cbe571a WD |
164 | |
165 | #define PHYS_FLASH_1 0x10000000 | |
9d5028c2 | 166 | #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
168 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
169 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
170 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
171 | #define CONFIG_SYS_FLASH_ERASE_TOUT (11 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ | |
172 | #define CONFIG_SYS_FLASH_WRITE_TOUT ( 2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
2cbe571a | 173 | |
5a1aceb0 | 174 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
175 | #define CONFIG_ENV_OFFSET 0x20000 /* after u-boot.bin */ |
176 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ | |
177 | #define CONFIG_ENV_SIZE (16 << 10) /* Use only 16 kB */ | |
2cbe571a | 178 | |
6d0f6bcf | 179 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ |
2cbe571a | 180 | |
6d0f6bcf | 181 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } |
2cbe571a | 182 | |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
184 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
185 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
186 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
2cbe571a | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_HZ 1000 |
189 | #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ | |
59acc296 | 190 | /* AT91C_TC_TIMER_DIV1_CLOCK */ |
2cbe571a WD |
191 | |
192 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
193 | ||
194 | #ifdef CONFIG_USE_IRQ | |
195 | #error CONFIG_USE_IRQ not supported | |
196 | #endif | |
197 | ||
3dd7f0f0 | 198 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
fe126d8b | 199 | "net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \ |
3dd7f0f0 WD |
200 | "addmtd;bootm\0" \ |
201 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b WD |
202 | "nfsroot=${serverip}:${rootpath}\0" \ |
203 | "net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \ | |
3dd7f0f0 WD |
204 | "addcons addmtd; bootm\0" \ |
205 | "flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \ | |
206 | "flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \ | |
fe126d8b WD |
207 | "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ |
208 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ | |
209 | "${hostname}::off\0" \ | |
210 | "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ | |
211 | "addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \ | |
3dd7f0f0 | 212 | "64k(environment),768k(linux),4096k(root),-\0" \ |
fe126d8b | 213 | "load=tftp ${loadaddr} ${loadfile}\0" \ |
3dd7f0f0 | 214 | "update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \ |
fe126d8b | 215 | "cp.b ${loadaddr} 10000000 ${filesize};" \ |
3dd7f0f0 | 216 | "protect on 10000000 1001ffff\0" \ |
fe126d8b WD |
217 | "updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \ |
218 | "cp.b ${loadaddr} 10030000 ${filesize}\0" \ | |
219 | "updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \ | |
220 | "cp.b ${loadaddr} 100f0000 ${filesize}\0" \ | |
221 | "updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \ | |
222 | "cp.b ${loadaddr} 104f0000 ${filesize}\0" \ | |
3dd7f0f0 WD |
223 | "cramfsimage=cramfs_cmc-pu2.img\0" \ |
224 | "jffsimage=jffs2_cmc-pu2.img\0" \ | |
225 | "loadfile=u-boot_cmc-pu2.bin\0" \ | |
226 | "bootfile=uImage_cmc-pu2\0" \ | |
227 | "loadaddr=0x20800000\0" \ | |
228 | "hostname=CMC-TC-PU2\0" \ | |
229 | "bootcmd=run dhcp_start;run flash_cramfs\0" \ | |
230 | "autoload=n\0" \ | |
231 | "dhcp_start=echo no DHCP\0" \ | |
232 | "ipaddr=192.168.0.190\0" | |
45ea3fca | 233 | #endif /* __CONFIG_H */ |