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2cbe571a | 1 | /* |
414eec35 | 2 | * 2004-2005 Gary Jennejohn <garyj@denx.de> |
2cbe571a | 3 | * |
9d5028c2 | 4 | * Configuration settings for the CMC PU2 board. |
2cbe571a WD |
5 | * |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
45ea3fca | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
2cbe571a WD |
17 | * GNU General Public License for more details. |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
2cbe571a | 28 | /* ARM asynchronous clock */ |
ed54e621 | 29 | #define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ |
101e8dfa | 30 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ |
2cbe571a WD |
31 | |
32 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | |
33 | ||
34 | #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ | |
45ea3fca | 35 | #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */ |
2cbe571a WD |
36 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
37 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
38 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
39 | #define CONFIG_INITRD_TAG 1 | |
40 | ||
8aa1a2d1 | 41 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
ef2807c6 WD |
42 | #define CFG_USE_MAIN_OSCILLATOR 1 |
43 | /* flash */ | |
44 | #define MC_PUIA_VAL 0x00000000 | |
45 | #define MC_PUP_VAL 0x00000000 | |
46 | #define MC_PUER_VAL 0x00000000 | |
47 | #define MC_ASR_VAL 0x00000000 | |
48 | #define MC_AASR_VAL 0x00000000 | |
49 | #define EBI_CFGR_VAL 0x00000000 | |
50 | #define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ | |
51 | ||
52 | /* clocks */ | |
53 | #define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */ | |
54 | #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ | |
55 | #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ | |
56 | ||
57 | /* sdram */ | |
58 | #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ | |
59 | #define PIOC_BSR_VAL 0x00000000 | |
60 | #define PIOC_PDR_VAL 0xFFFF0000 | |
61 | #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ | |
62 | #define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ | |
63 | #define SDRAM 0x20000000 /* address of the SDRAM */ | |
64 | #define SDRAM1 0x20000080 /* address of the SDRAM */ | |
65 | #define SDRAM_VAL 0x00000000 /* value written to SDRAM */ | |
66 | #define SDRC_MR_VAL 0x00000002 /* Precharge All */ | |
67 | #define SDRC_MR_VAL1 0x00000004 /* refresh */ | |
68 | #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ | |
69 | #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ | |
70 | #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ | |
8aa1a2d1 | 71 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
ef2807c6 | 72 | |
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73 | /* |
74 | * Size of malloc() pool | |
75 | */ | |
76 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) | |
77 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
78 | ||
45ea3fca | 79 | #define CONFIG_BAUDRATE 9600 |
2cbe571a | 80 | |
ed54e621 | 81 | #define CFG_AT91C_BRGR_DIVISOR 450 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */ |
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82 | |
83 | /* | |
84 | * Hardware drivers | |
85 | */ | |
86 | ||
87 | /* define one of these to choose the DBGU, USART0 or USART1 as console */ | |
88 | #undef CONFIG_DBGU | |
9d5028c2 WD |
89 | #define CONFIG_USART0 |
90 | #undef CONFIG_USART1 | |
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91 | |
92 | #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ | |
93 | ||
94 | #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ | |
95 | ||
9d5028c2 | 96 | #define CONFIG_HARD_I2C |
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97 | |
98 | #ifdef CONFIG_HARD_I2C | |
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99 | #define CFG_I2C_SPEED 0 /* not used */ |
100 | #define CFG_I2C_SLAVE 0 /* not used */ | |
101 | #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */ | |
102 | #define CFG_I2C_RTC_ADDR 0x32 | |
103 | #define CFG_I2C_EEPROM_ADDR 0x50 | |
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104 | #define CFG_I2C_EEPROM_ADDR_LEN 1 |
105 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW | |
106 | #endif | |
ed54e621 WD |
107 | /* still about 20 kB free with this defined */ |
108 | #define CFG_LONGHELP | |
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109 | |
110 | #define CONFIG_BOOTDELAY 3 | |
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111 | |
112 | #ifdef CONFIG_HARD_I2C | |
113 | #define CONFIG_COMMANDS \ | |
45ea3fca | 114 | ((CONFIG_CMD_DFL | \ |
45ea3fca | 115 | CFG_CMD_DATE | \ |
414eec35 | 116 | CFG_CMD_DHCP | \ |
45ea3fca | 117 | CFG_CMD_EEPROM | \ |
414eec35 WD |
118 | CFG_CMD_I2C | \ |
119 | CFG_CMD_NFS | \ | |
120 | CFG_CMD_SNTP ) & \ | |
45ea3fca | 121 | ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) |
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122 | #else |
123 | #define CONFIG_COMMANDS \ | |
45ea3fca | 124 | ((CONFIG_CMD_DFL | \ |
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125 | CFG_CMD_DHCP | \ |
126 | CFG_CMD_NFS | \ | |
127 | CFG_CMD_SNTP ) & \ | |
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128 | ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) |
129 | #define CONFIG_TIMESTAMP | |
2cbe571a | 130 | #endif |
ed54e621 | 131 | #define CFG_LONGHELP |
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132 | |
133 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
134 | #include <cmd_confdefs.h> | |
135 | ||
45ea3fca WD |
136 | #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ |
137 | #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ | |
2cbe571a | 138 | |
45ea3fca WD |
139 | #define CONFIG_NR_DRAM_BANKS 1 |
140 | #define PHYS_SDRAM 0x20000000 | |
141 | #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ | |
2cbe571a WD |
142 | |
143 | #define CFG_MEMTEST_START PHYS_SDRAM | |
144 | #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 | |
145 | ||
146 | #define CONFIG_DRIVER_ETHER | |
147 | #define CONFIG_NET_RETRY_COUNT 20 | |
148 | #define CONFIG_AT91C_USE_RMII | |
149 | ||
150 | #define CONFIG_HAS_DATAFLASH 1 | |
151 | #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) | |
45ea3fca WD |
152 | #define CFG_MAX_DATAFLASH_BANKS 2 |
153 | #define CFG_MAX_DATAFLASH_PAGES 16384 | |
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154 | #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ |
155 | #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ | |
156 | ||
157 | #define PHYS_FLASH_1 0x10000000 | |
9d5028c2 | 158 | #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */ |
2cbe571a | 159 | #define CFG_FLASH_BASE PHYS_FLASH_1 |
45ea3fca | 160 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
2cbe571a WD |
161 | #define CFG_MAX_FLASH_BANKS 1 |
162 | #define CFG_MAX_FLASH_SECT 256 | |
e6ba3c92 WD |
163 | #define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */ |
164 | #define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */ | |
2cbe571a | 165 | |
2cbe571a | 166 | #define CFG_ENV_IS_IN_FLASH 1 |
45ea3fca WD |
167 | #define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */ |
168 | #define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */ | |
169 | #define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */ | |
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170 | |
171 | #define CFG_LOAD_ADDR 0x21000000 /* default load address */ | |
172 | ||
45ea3fca | 173 | #define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } |
2cbe571a | 174 | |
45ea3fca | 175 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
2cbe571a | 176 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
45ea3fca | 177 | #define CFG_MAXARGS 32 /* max number of command args */ |
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178 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
179 | ||
180 | #ifndef __ASSEMBLY__ | |
181 | /*----------------------------------------------------------------------- | |
182 | * Board specific extension for bd_info | |
183 | * | |
184 | * This structure is embedded in the global bd_info (bd_t) structure | |
185 | * and can be used by the board specific code (eg board/...) | |
186 | */ | |
187 | ||
188 | struct bd_info_ext { | |
189 | /* helper variable for board environment handling | |
190 | * | |
45ea3fca WD |
191 | * env_crc_valid == 0 => uninitialised |
192 | * env_crc_valid > 0 => environment crc in flash is valid | |
193 | * env_crc_valid < 0 => environment crc in flash is invalid | |
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194 | */ |
195 | int env_crc_valid; | |
196 | }; | |
45ea3fca | 197 | #endif /* __ASSEMBLY__ */ |
2cbe571a | 198 | |
9455b7f3 | 199 | #define CFG_HZ 1000 |
101e8dfa | 200 | #define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ |
59acc296 | 201 | /* AT91C_TC_TIMER_DIV1_CLOCK */ |
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202 | |
203 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
204 | ||
205 | #ifdef CONFIG_USE_IRQ | |
206 | #error CONFIG_USE_IRQ not supported | |
207 | #endif | |
208 | ||
45ea3fca | 209 | #endif /* __CONFIG_H */ |