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a562e1bd WD |
1 | /* |
2 | * Configuation settings for the Sentec Cobra Board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* --- | |
26 | * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board | |
27 | * Date: 2004-03-29 | |
28 | * Author: Florian Schlote | |
29 | * | |
30 | * For a description of configuration options please refer also to the | |
31 | * general u-boot-1.x.x/README file | |
32 | * --- | |
33 | */ | |
34 | ||
35 | /* --- | |
36 | * board/config.h - configuration options, board specific | |
37 | * --- | |
38 | */ | |
39 | ||
40 | #ifndef _CONFIG_COBRA5272_H | |
41 | #define _CONFIG_COBRA5272_H | |
42 | ||
43 | /* --- | |
44 | * Define processor | |
45 | * possible values for Sentec board: only Coldfire M5272 processor supported | |
46 | * (please do not change) | |
47 | * --- | |
48 | */ | |
49 | ||
50 | #define CONFIG_MCF52x2 /* define processor family */ | |
51 | #define CONFIG_M5272 /* define processor type */ | |
52 | ||
53 | /* --- | |
54 | * Defines processor clock - important for correct timings concerning serial | |
55 | * interface etc. | |
6d0f6bcf | 56 | * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms |
a562e1bd WD |
57 | * --- |
58 | */ | |
59 | ||
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_HZ 1000 |
61 | #define CONFIG_SYS_CLK 66000000 | |
62 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
a562e1bd WD |
63 | |
64 | /* --- | |
65 | * Enable use of Ethernet | |
66 | * --- | |
67 | */ | |
6706424d | 68 | #define CONFIG_MCFFEC |
a562e1bd | 69 | |
6706424d TL |
70 | /* Enable Dma Timer */ |
71 | #define CONFIG_MCFTMR | |
a562e1bd WD |
72 | |
73 | /* --- | |
74 | * Define baudrate for UART1 (console output, tftp, ...) | |
75 | * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud | |
6d0f6bcf | 76 | * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command |
a562e1bd WD |
77 | * interface |
78 | * --- | |
79 | */ | |
80 | ||
6706424d | 81 | #define CONFIG_MCFUART |
6d0f6bcf | 82 | #define CONFIG_SYS_UART_PORT (0) |
a562e1bd | 83 | #define CONFIG_BAUDRATE 19200 |
6d0f6bcf | 84 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
a562e1bd WD |
85 | |
86 | /* --- | |
87 | * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change | |
88 | * timeout acc. to your needs | |
89 | * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 | |
90 | * for 10 sec | |
91 | * --- | |
92 | */ | |
93 | ||
94 | #if 0 | |
95 | #define CONFIG_WATCHDOG | |
96 | #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ | |
97 | #endif | |
98 | ||
99 | /* --- | |
100 | * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different | |
101 | * bootloader residing in flash ('chainloading'); if you want to use | |
102 | * chainloading or want to compile a u-boot binary that can be loaded into | |
103 | * RAM via BDM set | |
53677ef1 | 104 | * "#if 0" to "#if 1" |
a562e1bd WD |
105 | * You will need a first stage bootloader then, e. g. colilo or a working BDM |
106 | * cable (Background Debug Mode) | |
107 | * | |
108 | * Setting #if 0: u-boot will start from flash and relocate itself to RAM | |
109 | * | |
110 | * Please do not forget to modify the setting of TEXT_BASE | |
111 | * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) | |
112 | * | |
113 | * --- | |
114 | */ | |
115 | ||
116 | #if 0 | |
117 | #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ | |
118 | #endif | |
119 | ||
120 | /* --- | |
121 | * Configuration for environment | |
122 | * Environment is embedded in u-boot in the second sector of the flash | |
123 | * --- | |
124 | */ | |
125 | ||
126 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
127 | #define CONFIG_ENV_OFFSET 0x4000 |
128 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 129 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a562e1bd | 130 | #else |
0e8d1586 JCPV |
131 | #define CONFIG_ENV_ADDR 0xffe04000 |
132 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 133 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a562e1bd WD |
134 | #endif |
135 | ||
37e4f24b | 136 | |
80ff4f99 JL |
137 | /* |
138 | * BOOTP options | |
139 | */ | |
140 | #define CONFIG_BOOTP_BOOTFILESIZE | |
141 | #define CONFIG_BOOTP_BOOTPATH | |
142 | #define CONFIG_BOOTP_GATEWAY | |
143 | #define CONFIG_BOOTP_HOSTNAME | |
144 | ||
145 | ||
37e4f24b JL |
146 | /* |
147 | * Command line configuration. | |
a562e1bd | 148 | */ |
37e4f24b JL |
149 | #include <config_cmd_default.h> |
150 | ||
151 | #define CONFIG_CMD_PING | |
a562e1bd | 152 | |
37e4f24b JL |
153 | #undef CONFIG_CMD_LOADS |
154 | #undef CONFIG_CMD_LOADB | |
155 | #undef CONFIG_CMD_MII | |
a562e1bd | 156 | |
6706424d TL |
157 | #ifdef CONFIG_MCFFEC |
158 | # define CONFIG_NET_MULTI 1 | |
159 | # define CONFIG_MII 1 | |
0f3ba7e9 | 160 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
161 | # define CONFIG_SYS_DISCOVER_PHY |
162 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
163 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
6706424d | 164 | |
6d0f6bcf JCPV |
165 | # define CONFIG_SYS_FEC0_PINMUX 0 |
166 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 167 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
168 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
169 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
6706424d TL |
170 | # define FECDUPLEX FULL |
171 | # define FECSPEED _100BASET | |
172 | # else | |
6d0f6bcf JCPV |
173 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
174 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
6706424d | 175 | # endif |
6d0f6bcf | 176 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
6706424d | 177 | #endif |
a562e1bd WD |
178 | |
179 | /* | |
180 | *----------------------------------------------------------------------------- | |
181 | * Define user parameters that have to be customized most likely | |
182 | *----------------------------------------------------------------------------- | |
183 | */ | |
184 | ||
185 | /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ | |
186 | ||
187 | #define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in | |
188 | seconds u-boot will wait before starting defined (auto-)boot command, setting | |
189 | to -1 disables delay, setting to 0 will too prevent access to u-boot command | |
190 | interface: u-boot then has to reflashed */ | |
191 | ||
192 | ||
193 | /* The following settings will be contained in the environment block ; if you | |
194 | want to use a neutral environment all those settings can be manually set in | |
195 | u-boot: 'set' command */ | |
196 | ||
197 | #if 0 | |
198 | ||
199 | #define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please | |
200 | enter a valid image address in flash */ | |
201 | ||
202 | #define CONFIG_BOOTARGS " " /* default bootargs that are | |
203 | considered during boot */ | |
204 | ||
205 | /* User network settings */ | |
206 | ||
207 | #define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */ | |
208 | #define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ | |
209 | #define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ | |
210 | ||
211 | #endif | |
212 | ||
6d0f6bcf | 213 | #define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/ |
a562e1bd | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address |
a562e1bd WD |
216 | from which user programs will be started */ |
217 | ||
218 | /*---*/ | |
219 | ||
6d0f6bcf | 220 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a562e1bd | 221 | |
37e4f24b | 222 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 223 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a562e1bd | 224 | #else |
6d0f6bcf | 225 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a562e1bd | 226 | #endif |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
228 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
229 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a562e1bd WD |
230 | |
231 | /* | |
232 | *----------------------------------------------------------------------------- | |
233 | * End of user parameters to be customized | |
234 | *----------------------------------------------------------------------------- | |
235 | */ | |
236 | ||
237 | /* --- | |
238 | * Defines memory range for test | |
239 | * --- | |
240 | */ | |
241 | ||
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_MEMTEST_START 0x400 |
243 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a562e1bd WD |
244 | |
245 | /* --- | |
246 | * Low Level Configuration Settings | |
247 | * (address mappings, register initial values, etc.) | |
248 | * You should know what you are doing if you make changes here. | |
249 | * --- | |
250 | */ | |
251 | ||
252 | /* --- | |
253 | * Base register address | |
254 | * --- | |
255 | */ | |
256 | ||
6d0f6bcf | 257 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
a562e1bd WD |
258 | |
259 | /* --- | |
260 | * System Conf. Reg. & System Protection Reg. | |
261 | * --- | |
262 | */ | |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_SCR 0x0003 |
265 | #define CONFIG_SYS_SPR 0xffff | |
a562e1bd WD |
266 | |
267 | /* --- | |
268 | * Ethernet settings | |
269 | * --- | |
270 | */ | |
271 | ||
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_DISCOVER_PHY |
273 | #define CONFIG_SYS_ENET_BD_BASE 0x780000 | |
a562e1bd WD |
274 | |
275 | /*----------------------------------------------------------------------- | |
276 | * Definitions for initial stack pointer and data area (in internal SRAM) | |
277 | */ | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
279 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ | |
280 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
281 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
282 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
a562e1bd WD |
283 | |
284 | /*----------------------------------------------------------------------- | |
285 | * Start addresses for the final memory configuration | |
286 | * (Set up by the startup code) | |
6d0f6bcf | 287 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a562e1bd | 288 | */ |
6d0f6bcf | 289 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
a562e1bd WD |
290 | |
291 | /* | |
292 | *------------------------------------------------------------------------- | |
293 | * RAM SIZE (is defined above) | |
294 | *----------------------------------------------------------------------- | |
295 | */ | |
296 | ||
6d0f6bcf | 297 | /* #define CONFIG_SYS_SDRAM_SIZE 16 */ |
a562e1bd WD |
298 | |
299 | /* | |
300 | *----------------------------------------------------------------------- | |
301 | */ | |
302 | ||
6d0f6bcf | 303 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
a562e1bd WD |
304 | |
305 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 306 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
a562e1bd | 307 | #else |
6d0f6bcf | 308 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a562e1bd WD |
309 | #endif |
310 | ||
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
312 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
313 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
a562e1bd WD |
314 | |
315 | /* | |
316 | * For booting Linux, the board info and command line data | |
317 | * have to be in the first 8 MB of memory, since this is | |
318 | * the maximum mapped by the Linux kernel during initialization ?? | |
319 | */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
a562e1bd WD |
321 | |
322 | /*----------------------------------------------------------------------- | |
323 | * FLASH organization | |
324 | */ | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
326 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
327 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ | |
a562e1bd WD |
328 | |
329 | /*----------------------------------------------------------------------- | |
330 | * Cache Configuration | |
331 | */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a562e1bd | 333 | |
dd9f054e TL |
334 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
335 | CONFIG_SYS_INIT_RAM_END - 8) | |
336 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
337 | CONFIG_SYS_INIT_RAM_END - 4) | |
338 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) | |
339 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
340 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
341 | CF_ACR_EN | CF_ACR_SM_ALL) | |
342 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
343 | CF_CACR_DISD | CF_CACR_INVI | \ | |
344 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
345 | CF_CACR_EUSP) | |
346 | ||
a562e1bd WD |
347 | /*----------------------------------------------------------------------- |
348 | * Memory bank definitions | |
349 | * | |
350 | * Please refer also to Motorola Coldfire user manual - Chapter XXX | |
351 | * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf> | |
352 | */ | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 |
354 | #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 | |
a562e1bd | 355 | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_BR1_PRELIM 0 |
357 | #define CONFIG_SYS_OR1_PRELIM 0 | |
a562e1bd | 358 | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_BR2_PRELIM 0 |
360 | #define CONFIG_SYS_OR2_PRELIM 0 | |
a562e1bd | 361 | |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_BR3_PRELIM 0 |
363 | #define CONFIG_SYS_OR3_PRELIM 0 | |
a562e1bd | 364 | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_BR4_PRELIM 0 |
366 | #define CONFIG_SYS_OR4_PRELIM 0 | |
a562e1bd | 367 | |
6d0f6bcf JCPV |
368 | #define CONFIG_SYS_BR5_PRELIM 0 |
369 | #define CONFIG_SYS_OR5_PRELIM 0 | |
a562e1bd | 370 | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_BR6_PRELIM 0 |
372 | #define CONFIG_SYS_OR6_PRELIM 0 | |
a562e1bd | 373 | |
6d0f6bcf JCPV |
374 | #define CONFIG_SYS_BR7_PRELIM 0x00000701 |
375 | #define CONFIG_SYS_OR7_PRELIM 0xFF00007C | |
a562e1bd WD |
376 | |
377 | /*----------------------------------------------------------------------- | |
378 | * LED config | |
379 | */ | |
380 | #define LED_STAT_0 0xffff /*all LEDs off*/ | |
381 | #define LED_STAT_1 0xfffe | |
382 | #define LED_STAT_2 0xfffd | |
383 | #define LED_STAT_3 0xfffb | |
384 | #define LED_STAT_4 0xfff7 | |
385 | #define LED_STAT_5 0xffef | |
386 | #define LED_STAT_6 0xffdf | |
387 | #define LED_STAT_7 0xff00 /*all LEDs on*/ | |
388 | ||
389 | /*----------------------------------------------------------------------- | |
390 | * Port configuration (GPIO) | |
391 | */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external |
a562e1bd | 393 | GPIO*/ |
6d0f6bcf | 394 | #define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs |
a562e1bd | 395 | (1^=output, 0^=input) */ |
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ |
397 | #define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART | |
a562e1bd | 398 | configuration */ |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ |
400 | #define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ | |
401 | #define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ | |
a562e1bd WD |
402 | |
403 | #endif /* _CONFIG_COBRA5272_H */ |