[people/ms/u-boot.git] / include / configs / cobra5272.h

/*
 * Configuation settings for the Sentec Cobra Board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ---
 * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
 * Date: 2004-03-29
 * Author: Florian Schlote
 *
 * For a description of configuration options please refer also to the
 * general u-boot-1.x.x/README file
 * ---
 */

/* ---
 * board/config.h - configuration options, board specific
 * ---
 */

#ifndef _CONFIG_COBRA5272_H
#define _CONFIG_COBRA5272_H

/* ---
 * Defines processor clock - important for correct timings concerning serial
 * interface etc.
 * ---
 */

#define CONFIG_SYS_CLK			66000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */

/* ---
 * Enable use of Ethernet
 * ---
 */
#define CONFIG_MCFFEC

/* Enable Dma Timer */
#define CONFIG_MCFTMR

/* ---
 * Define baudrate for UART1 (console output, tftp, ...)
 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
 * interface
 * ---
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		19200

/* ---
 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
 * timeout acc. to your needs
 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
 * for 10 sec
 * ---
 */

#if 0
#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
#endif

/* ---
 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
 * bootloader residing in flash ('chainloading'); if you want to use
 * chainloading or want to compile a u-boot binary that can be loaded into
 * RAM via BDM set
 *	"#if 0" to "#if 1"
 * You will need a first stage bootloader then, e. g. colilo or a working BDM
 * cable (Background Debug Mode)
 *
 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
 *
 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
 *
 * ---
 */

#if 0
#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
#endif

/* ---
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 * ---
 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_PING

#undef CONFIG_CMD_MII

#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/*
 *-----------------------------------------------------------------------------
 * Define user parameters that have to be customized most likely
 *-----------------------------------------------------------------------------
 */

/*AUTOBOOT settings - booting images automatically by u-boot after power on*/

#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
seconds u-boot will wait before starting defined (auto-)boot command, setting
to -1 disables delay, setting to 0 will too prevent access to u-boot command
interface: u-boot then has to reflashed */


/* The following settings will be contained in the environment block ; if you
want to use a neutral environment all those settings can be manually set in
u-boot: 'set' command */

#if 0

#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
enter a valid image address in flash */

#define CONFIG_BOOTARGS		" "			/* default bootargs that are
considered during boot */

/* User network settings */

#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */

#endif

#define CONFIG_SYS_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/

#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
from which user programs will be started */

/*---*/

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

/*
 *-----------------------------------------------------------------------------
 * End of user parameters to be customized
 *-----------------------------------------------------------------------------
 */

/* ---
 * Defines memory range for test
 * ---
 */

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

/* ---
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * ---
 */

/* ---
 * Base register address
 * ---
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */

/* ---
 * System Conf. Reg. & System Protection Reg.
 * ---
 */

#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/* ---
 * Ethernet settings
 * ---
 */

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_ENET_BD_BASE	0x780000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in internal SRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000

/*
 *-------------------------------------------------------------------------
 * RAM SIZE (is defined above)
 *-----------------------------------------------------------------------
 */

/* #define CONFIG_SYS_SDRAM_SIZE		16 */

/*
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 *
 * Please refer also to Motorola Coldfire user manual - Chapter XXX
 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014

#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0

#define CONFIG_SYS_BR2_PRELIM		0
#define CONFIG_SYS_OR2_PRELIM		0

#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0

#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0

#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0

#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0

#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFF00007C

/*-----------------------------------------------------------------------
 * LED config
 */
#define	LED_STAT_0	0xffff /*all LEDs off*/
#define	LED_STAT_1	0xfffe
#define	LED_STAT_2	0xfffd
#define	LED_STAT_3	0xfffb
#define	LED_STAT_4	0xfff7
#define	LED_STAT_5	0xffef
#define	LED_STAT_6	0xffdf
#define	LED_STAT_7	0xff00 /*all LEDs on*/

/*-----------------------------------------------------------------------
 * Port configuration (GPIO)
 */
#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
GPIO*/
#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
(1^=output, 0^=input) */
#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
configuration */
#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */

#endif	/* _CONFIG_COBRA5272_H */
Commit	Line	Data
a562e1bd WD	1	/*
	2	* Configuation settings for the Sentec Cobra Board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
a562e1bd WD	7	*/
	8
	9	/* ---
	10	* Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
	11	* Date: 2004-03-29
	12	* Author: Florian Schlote
	13	*
	14	* For a description of configuration options please refer also to the
	15	* general u-boot-1.x.x/README file
	16	* ---
	17	*/
	18
	19	/* ---
	20	* board/config.h - configuration options, board specific
	21	* ---
	22	*/
	23
	24	#ifndef _CONFIG_COBRA5272_H
	25	#define _CONFIG_COBRA5272_H
	26
a562e1bd WD	27	/* ---
	28	* Defines processor clock - important for correct timings concerning serial
	29	* interface etc.
a562e1bd WD	30	* ---
	31	*/
	32
6d0f6bcf JCPV	33	#define CONFIG_SYS_CLK 66000000
6d0f6bcf JCPV	34	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
a562e1bd WD	35
	36	/* ---
	37	* Enable use of Ethernet
	38	* ---
	39	*/
6706424d	40	#define CONFIG_MCFFEC
a562e1bd	41
6706424d TL	42	/* Enable Dma Timer */
6706424d TL	43	#define CONFIG_MCFTMR
a562e1bd WD	44
	45	/* ---
	46	* Define baudrate for UART1 (console output, tftp, ...)
	47	* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
6d0f6bcf	48	* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
a562e1bd WD	49	* interface
	50	* ---
	51	*/
	52
6706424d	53	#define CONFIG_MCFUART
6d0f6bcf	54	#define CONFIG_SYS_UART_PORT (0)
a562e1bd	55	#define CONFIG_BAUDRATE 19200
a562e1bd WD	56
	57	/* ---
	58	* set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
	59	* timeout acc. to your needs
	60	* #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
	61	* for 10 sec
	62	* ---
	63	*/
	64
	65	#if 0
	66	#define CONFIG_WATCHDOG
	67	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
	68	#endif
	69
	70	/* ---
	71	* CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
	72	* bootloader residing in flash ('chainloading'); if you want to use
	73	* chainloading or want to compile a u-boot binary that can be loaded into
	74	* RAM via BDM set
53677ef1	75	* "#if 0" to "#if 1"
a562e1bd WD	76	* You will need a first stage bootloader then, e. g. colilo or a working BDM
	77	* cable (Background Debug Mode)
	78	*
	79	* Setting #if 0: u-boot will start from flash and relocate itself to RAM
	80	*
14d0a02a	81	* Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
a562e1bd WD	82	* in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
	83	*
	84	* ---
	85	*/
	86
	87	#if 0
	88	#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
	89	#endif
	90
	91	/* ---
	92	* Configuration for environment
	93	* Environment is embedded in u-boot in the second sector of the flash
	94	* ---
	95	*/
	96
	97	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	98	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	99	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	100	#define CONFIG_ENV_IS_IN_FLASH 1
a562e1bd	101	#else
0e8d1586 JCPV	102	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	103	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	104	#define CONFIG_ENV_IS_IN_FLASH 1
a562e1bd WD	105	#endif
a562e1bd WD	106
5296cb1d	107	#define LDS_BOARD_TEXT \
	108	. = DEFINED(env_offset) ? env_offset : .; \
	109	common/env_embedded.o (.text);
37e4f24b	110
80ff4f99 JL	111	/*
	112	* BOOTP options
	113	*/
	114	#define CONFIG_BOOTP_BOOTFILESIZE
	115	#define CONFIG_BOOTP_BOOTPATH
	116	#define CONFIG_BOOTP_GATEWAY
	117	#define CONFIG_BOOTP_HOSTNAME
	118
	119
37e4f24b JL	120	/*
37e4f24b JL	121	* Command line configuration.
a562e1bd	122	*/
37e4f24b	123	#define CONFIG_CMD_PING
a562e1bd	124
37e4f24b	125	#undef CONFIG_CMD_MII
a562e1bd	126
6706424d	127	#ifdef CONFIG_MCFFEC
6706424d	128	# define CONFIG_MII 1
0f3ba7e9	129	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	130	# define CONFIG_SYS_DISCOVER_PHY
	131	# define CONFIG_SYS_RX_ETH_BUFFER 8
	132	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	133
6d0f6bcf JCPV	134	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	135	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	136	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	137	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	138	# ifndef CONFIG_SYS_DISCOVER_PHY
6706424d TL	139	# define FECDUPLEX FULL
	140	# define FECSPEED _100BASET
	141	# else
6d0f6bcf JCPV	142	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	143	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	144	# endif
6d0f6bcf	145	# endif /* CONFIG_SYS_DISCOVER_PHY */
6706424d	146	#endif
a562e1bd WD	147
	148	/*
	149	*-----------------------------------------------------------------------------
	150	* Define user parameters that have to be customized most likely
	151	*-----------------------------------------------------------------------------
	152	*/
	153
	154	/AUTOBOOT settings - booting images automatically by u-boot after power on/
	155
	156	#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in
	157	seconds u-boot will wait before starting defined (auto-)boot command, setting
	158	to -1 disables delay, setting to 0 will too prevent access to u-boot command
	159	interface: u-boot then has to reflashed */
	160
	161
	162	/* The following settings will be contained in the environment block ; if you
	163	want to use a neutral environment all those settings can be manually set in
	164	u-boot: 'set' command */
	165
	166	#if 0
	167
	168	#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
	169	enter a valid image address in flash */
	170
	171	#define CONFIG_BOOTARGS " " /* default bootargs that are
	172	considered during boot */
	173
	174	/* User network settings */
	175
a562e1bd WD	176	#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
	177	#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
	178
	179	#endif
	180
6d0f6bcf	181	#define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/
a562e1bd	182
6d0f6bcf	183	#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
a562e1bd WD	184	from which user programs will be started */
	185
	186	/---/
	187
6d0f6bcf	188	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a562e1bd	189
37e4f24b	190	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	191	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a562e1bd	192	#else
6d0f6bcf	193	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a562e1bd	194	#endif
6d0f6bcf JCPV	195	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	196	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	197	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a562e1bd WD	198
	199	/*
	200	*-----------------------------------------------------------------------------
	201	* End of user parameters to be customized
	202	*-----------------------------------------------------------------------------
	203	*/
	204
	205	/* ---
	206	* Defines memory range for test
	207	* ---
	208	*/
	209
6d0f6bcf JCPV	210	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	211	#define CONFIG_SYS_MEMTEST_END 0x380000
a562e1bd WD	212
	213	/* ---
	214	* Low Level Configuration Settings
	215	* (address mappings, register initial values, etc.)
	216	* You should know what you are doing if you make changes here.
	217	* ---
	218	*/
	219
	220	/* ---
	221	* Base register address
	222	* ---
	223	*/
	224
6d0f6bcf	225	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
a562e1bd WD	226
	227	/* ---
	228	* System Conf. Reg. & System Protection Reg.
	229	* ---
	230	*/
	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_SCR 0x0003
6d0f6bcf JCPV	233	#define CONFIG_SYS_SPR 0xffff
a562e1bd WD	234
	235	/* ---
	236	* Ethernet settings
	237	* ---
	238	*/
	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_DISCOVER_PHY
6d0f6bcf JCPV	241	#define CONFIG_SYS_ENET_BD_BASE 0x780000
a562e1bd WD	242
	243	/*-----------------------------------------------------------------------
	244	* Definitions for initial stack pointer and data area (in internal SRAM)
	245	*/
6d0f6bcf	246	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	247	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	248	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	249	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a562e1bd WD	250
	251	/*-----------------------------------------------------------------------
	252	* Start addresses for the final memory configuration
	253	* (Set up by the startup code)
6d0f6bcf	254	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a562e1bd	255	*/
6d0f6bcf	256	#define CONFIG_SYS_SDRAM_BASE 0x00000000
a562e1bd WD	257
	258	/*
	259	*-------------------------------------------------------------------------
	260	* RAM SIZE (is defined above)
	261	*-----------------------------------------------------------------------
	262	*/
	263
6d0f6bcf	264	/* #define CONFIG_SYS_SDRAM_SIZE 16 */
a562e1bd WD	265
	266	/*
	267	*-----------------------------------------------------------------------
	268	*/
	269
6d0f6bcf	270	#define CONFIG_SYS_FLASH_BASE 0xffe00000
a562e1bd WD	271
a562e1bd WD	272	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	273	#define CONFIG_SYS_MONITOR_BASE 0x20000
a562e1bd	274	#else
6d0f6bcf	275	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a562e1bd WD	276	#endif
a562e1bd WD	277
6d0f6bcf JCPV	278	#define CONFIG_SYS_MONITOR_LEN 0x20000
	279	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	280	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a562e1bd WD	281
	282	/*
	283	* For booting Linux, the board info and command line data
	284	* have to be in the first 8 MB of memory, since this is
	285	* the maximum mapped by the Linux kernel during initialization ??
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a562e1bd WD	288
	289	/*-----------------------------------------------------------------------
	290	* FLASH organization
	291	*/
6d0f6bcf JCPV	292	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	293	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	294	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
a562e1bd WD	295
	296	/*-----------------------------------------------------------------------
	297	* Cache Configuration
	298	*/
6d0f6bcf	299	#define CONFIG_SYS_CACHELINE_SIZE 16
a562e1bd	300
dd9f054e	301	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	302	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	303	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	304	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	305	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	306	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	307	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	308	CF_ACR_EN \| CF_ACR_SM_ALL)
	309	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	310	CF_CACR_DISD \| CF_CACR_INVI \| \
	311	CF_CACR_CEIB \| CF_CACR_DCM \| \
	312	CF_CACR_EUSP)
	313
a562e1bd WD	314	/*-----------------------------------------------------------------------
	315	* Memory bank definitions
	316	*
	317	* Please refer also to Motorola Coldfire user manual - Chapter XXX
	318	* <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
	319	*/
6d0f6bcf JCPV	320	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
6d0f6bcf JCPV	321	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
a562e1bd	322
6d0f6bcf JCPV	323	#define CONFIG_SYS_BR1_PRELIM 0
6d0f6bcf JCPV	324	#define CONFIG_SYS_OR1_PRELIM 0
a562e1bd	325
6d0f6bcf JCPV	326	#define CONFIG_SYS_BR2_PRELIM 0
6d0f6bcf JCPV	327	#define CONFIG_SYS_OR2_PRELIM 0
a562e1bd	328
6d0f6bcf JCPV	329	#define CONFIG_SYS_BR3_PRELIM 0
6d0f6bcf JCPV	330	#define CONFIG_SYS_OR3_PRELIM 0
a562e1bd	331
6d0f6bcf JCPV	332	#define CONFIG_SYS_BR4_PRELIM 0
6d0f6bcf JCPV	333	#define CONFIG_SYS_OR4_PRELIM 0
a562e1bd	334
6d0f6bcf JCPV	335	#define CONFIG_SYS_BR5_PRELIM 0
6d0f6bcf JCPV	336	#define CONFIG_SYS_OR5_PRELIM 0
a562e1bd	337
6d0f6bcf JCPV	338	#define CONFIG_SYS_BR6_PRELIM 0
6d0f6bcf JCPV	339	#define CONFIG_SYS_OR6_PRELIM 0
a562e1bd	340
6d0f6bcf JCPV	341	#define CONFIG_SYS_BR7_PRELIM 0x00000701
6d0f6bcf JCPV	342	#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
a562e1bd WD	343
	344	/*-----------------------------------------------------------------------
	345	* LED config
	346	*/
	347	#define LED_STAT_0 0xffff /all LEDs off/
	348	#define LED_STAT_1 0xfffe
	349	#define LED_STAT_2 0xfffd
	350	#define LED_STAT_3 0xfffb
	351	#define LED_STAT_4 0xfff7
	352	#define LED_STAT_5 0xffef
	353	#define LED_STAT_6 0xffdf
	354	#define LED_STAT_7 0xff00 /all LEDs on/
	355
	356	/*-----------------------------------------------------------------------
	357	* Port configuration (GPIO)
	358	*/
6d0f6bcf	359	#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
a562e1bd	360	GPIO*/
6d0f6bcf	361	#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
a562e1bd	362	(1^=output, 0^=input) */
6d0f6bcf JCPV	363	#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
6d0f6bcf JCPV	364	#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
a562e1bd	365	configuration */
6d0f6bcf JCPV	366	#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
	367	#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
	368	#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
a562e1bd WD	369
a562e1bd WD	370	#endif /* _CONFIG_COBRA5272_H */