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a562e1bd WD |
1 | /* |
2 | * Configuation settings for the Sentec Cobra Board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
a562e1bd WD |
7 | */ |
8 | ||
9 | /* --- | |
a187559e | 10 | * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board |
a562e1bd WD |
11 | * Date: 2004-03-29 |
12 | * Author: Florian Schlote | |
13 | * | |
14 | * For a description of configuration options please refer also to the | |
15 | * general u-boot-1.x.x/README file | |
16 | * --- | |
17 | */ | |
18 | ||
19 | /* --- | |
20 | * board/config.h - configuration options, board specific | |
21 | * --- | |
22 | */ | |
23 | ||
24 | #ifndef _CONFIG_COBRA5272_H | |
25 | #define _CONFIG_COBRA5272_H | |
26 | ||
a562e1bd WD |
27 | /* --- |
28 | * Defines processor clock - important for correct timings concerning serial | |
29 | * interface etc. | |
a562e1bd WD |
30 | * --- |
31 | */ | |
32 | ||
6d0f6bcf JCPV |
33 | #define CONFIG_SYS_CLK 66000000 |
34 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
a562e1bd WD |
35 | |
36 | /* --- | |
37 | * Enable use of Ethernet | |
38 | * --- | |
39 | */ | |
6706424d | 40 | #define CONFIG_MCFFEC |
a562e1bd | 41 | |
6706424d TL |
42 | /* Enable Dma Timer */ |
43 | #define CONFIG_MCFTMR | |
a562e1bd WD |
44 | |
45 | /* --- | |
46 | * Define baudrate for UART1 (console output, tftp, ...) | |
47 | * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud | |
6d0f6bcf | 48 | * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command |
a562e1bd WD |
49 | * interface |
50 | * --- | |
51 | */ | |
52 | ||
6706424d | 53 | #define CONFIG_MCFUART |
6d0f6bcf | 54 | #define CONFIG_SYS_UART_PORT (0) |
a562e1bd WD |
55 | |
56 | /* --- | |
57 | * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change | |
58 | * timeout acc. to your needs | |
59 | * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 | |
60 | * for 10 sec | |
61 | * --- | |
62 | */ | |
63 | ||
64 | #if 0 | |
65 | #define CONFIG_WATCHDOG | |
66 | #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ | |
67 | #endif | |
68 | ||
69 | /* --- | |
70 | * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different | |
71 | * bootloader residing in flash ('chainloading'); if you want to use | |
72 | * chainloading or want to compile a u-boot binary that can be loaded into | |
73 | * RAM via BDM set | |
53677ef1 | 74 | * "#if 0" to "#if 1" |
a562e1bd WD |
75 | * You will need a first stage bootloader then, e. g. colilo or a working BDM |
76 | * cable (Background Debug Mode) | |
77 | * | |
78 | * Setting #if 0: u-boot will start from flash and relocate itself to RAM | |
79 | * | |
14d0a02a | 80 | * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE |
a562e1bd WD |
81 | * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) |
82 | * | |
83 | * --- | |
84 | */ | |
85 | ||
86 | #if 0 | |
87 | #define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ | |
88 | #endif | |
89 | ||
90 | /* --- | |
91 | * Configuration for environment | |
92 | * Environment is embedded in u-boot in the second sector of the flash | |
93 | * --- | |
94 | */ | |
95 | ||
96 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
97 | #define CONFIG_ENV_OFFSET 0x4000 |
98 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 99 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a562e1bd | 100 | #else |
0e8d1586 JCPV |
101 | #define CONFIG_ENV_ADDR 0xffe04000 |
102 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 103 | #define CONFIG_ENV_IS_IN_FLASH 1 |
a562e1bd WD |
104 | #endif |
105 | ||
5296cb1d | 106 | #define LDS_BOARD_TEXT \ |
107 | . = DEFINED(env_offset) ? env_offset : .; \ | |
108 | common/env_embedded.o (.text); | |
37e4f24b | 109 | |
80ff4f99 JL |
110 | /* |
111 | * BOOTP options | |
112 | */ | |
113 | #define CONFIG_BOOTP_BOOTFILESIZE | |
114 | #define CONFIG_BOOTP_BOOTPATH | |
115 | #define CONFIG_BOOTP_GATEWAY | |
116 | #define CONFIG_BOOTP_HOSTNAME | |
117 | ||
37e4f24b JL |
118 | /* |
119 | * Command line configuration. | |
a562e1bd WD |
120 | */ |
121 | ||
6706424d | 122 | #ifdef CONFIG_MCFFEC |
6706424d | 123 | # define CONFIG_MII 1 |
0f3ba7e9 | 124 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
125 | # define CONFIG_SYS_DISCOVER_PHY |
126 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
127 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
6706424d | 128 | |
6d0f6bcf JCPV |
129 | # define CONFIG_SYS_FEC0_PINMUX 0 |
130 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 131 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
132 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
133 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
6706424d TL |
134 | # define FECDUPLEX FULL |
135 | # define FECSPEED _100BASET | |
136 | # else | |
6d0f6bcf JCPV |
137 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
138 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
6706424d | 139 | # endif |
6d0f6bcf | 140 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
6706424d | 141 | #endif |
a562e1bd WD |
142 | |
143 | /* | |
144 | *----------------------------------------------------------------------------- | |
145 | * Define user parameters that have to be customized most likely | |
146 | *----------------------------------------------------------------------------- | |
147 | */ | |
148 | ||
149 | /*AUTOBOOT settings - booting images automatically by u-boot after power on*/ | |
150 | ||
a562e1bd WD |
151 | /* The following settings will be contained in the environment block ; if you |
152 | want to use a neutral environment all those settings can be manually set in | |
153 | u-boot: 'set' command */ | |
154 | ||
155 | #if 0 | |
156 | ||
157 | #define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please | |
158 | enter a valid image address in flash */ | |
159 | ||
160 | #define CONFIG_BOOTARGS " " /* default bootargs that are | |
161 | considered during boot */ | |
162 | ||
163 | /* User network settings */ | |
164 | ||
a562e1bd WD |
165 | #define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ |
166 | #define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ | |
167 | ||
168 | #endif | |
169 | ||
6d0f6bcf | 170 | #define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address |
a562e1bd WD |
171 | from which user programs will be started */ |
172 | ||
173 | /*---*/ | |
174 | ||
6d0f6bcf | 175 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a562e1bd | 176 | |
37e4f24b | 177 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 178 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a562e1bd | 179 | #else |
6d0f6bcf | 180 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a562e1bd | 181 | #endif |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
183 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
184 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a562e1bd WD |
185 | |
186 | /* | |
187 | *----------------------------------------------------------------------------- | |
188 | * End of user parameters to be customized | |
189 | *----------------------------------------------------------------------------- | |
190 | */ | |
191 | ||
192 | /* --- | |
193 | * Defines memory range for test | |
194 | * --- | |
195 | */ | |
196 | ||
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_MEMTEST_START 0x400 |
198 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a562e1bd WD |
199 | |
200 | /* --- | |
201 | * Low Level Configuration Settings | |
202 | * (address mappings, register initial values, etc.) | |
203 | * You should know what you are doing if you make changes here. | |
204 | * --- | |
205 | */ | |
206 | ||
207 | /* --- | |
208 | * Base register address | |
209 | * --- | |
210 | */ | |
211 | ||
6d0f6bcf | 212 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
a562e1bd WD |
213 | |
214 | /* --- | |
215 | * System Conf. Reg. & System Protection Reg. | |
216 | * --- | |
217 | */ | |
218 | ||
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_SCR 0x0003 |
220 | #define CONFIG_SYS_SPR 0xffff | |
a562e1bd WD |
221 | |
222 | /* --- | |
223 | * Ethernet settings | |
224 | * --- | |
225 | */ | |
226 | ||
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_DISCOVER_PHY |
228 | #define CONFIG_SYS_ENET_BD_BASE 0x780000 | |
a562e1bd WD |
229 | |
230 | /*----------------------------------------------------------------------- | |
231 | * Definitions for initial stack pointer and data area (in internal SRAM) | |
232 | */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 234 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
25ddd1fb | 235 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 236 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a562e1bd WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * Start addresses for the final memory configuration | |
240 | * (Set up by the startup code) | |
6d0f6bcf | 241 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a562e1bd | 242 | */ |
6d0f6bcf | 243 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
a562e1bd WD |
244 | |
245 | /* | |
246 | *------------------------------------------------------------------------- | |
247 | * RAM SIZE (is defined above) | |
248 | *----------------------------------------------------------------------- | |
249 | */ | |
250 | ||
6d0f6bcf | 251 | /* #define CONFIG_SYS_SDRAM_SIZE 16 */ |
a562e1bd WD |
252 | |
253 | /* | |
254 | *----------------------------------------------------------------------- | |
255 | */ | |
256 | ||
6d0f6bcf | 257 | #define CONFIG_SYS_FLASH_BASE 0xffe00000 |
a562e1bd WD |
258 | |
259 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 260 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
a562e1bd | 261 | #else |
6d0f6bcf | 262 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a562e1bd WD |
263 | #endif |
264 | ||
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
266 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
267 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
a562e1bd WD |
268 | |
269 | /* | |
270 | * For booting Linux, the board info and command line data | |
271 | * have to be in the first 8 MB of memory, since this is | |
272 | * the maximum mapped by the Linux kernel during initialization ?? | |
273 | */ | |
6d0f6bcf | 274 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
a562e1bd WD |
275 | |
276 | /*----------------------------------------------------------------------- | |
277 | * FLASH organization | |
278 | */ | |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
280 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
281 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ | |
a562e1bd WD |
282 | |
283 | /*----------------------------------------------------------------------- | |
284 | * Cache Configuration | |
285 | */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a562e1bd | 287 | |
dd9f054e | 288 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 289 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 290 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 291 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
292 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
293 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
294 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
295 | CF_ACR_EN | CF_ACR_SM_ALL) | |
296 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
297 | CF_CACR_DISD | CF_CACR_INVI | \ | |
298 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
299 | CF_CACR_EUSP) | |
300 | ||
a562e1bd WD |
301 | /*----------------------------------------------------------------------- |
302 | * Memory bank definitions | |
303 | * | |
304 | * Please refer also to Motorola Coldfire user manual - Chapter XXX | |
305 | * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf> | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_BR0_PRELIM 0xFFE00201 |
308 | #define CONFIG_SYS_OR0_PRELIM 0xFFE00014 | |
a562e1bd | 309 | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_BR1_PRELIM 0 |
311 | #define CONFIG_SYS_OR1_PRELIM 0 | |
a562e1bd | 312 | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_BR2_PRELIM 0 |
314 | #define CONFIG_SYS_OR2_PRELIM 0 | |
a562e1bd | 315 | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_BR3_PRELIM 0 |
317 | #define CONFIG_SYS_OR3_PRELIM 0 | |
a562e1bd | 318 | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_BR4_PRELIM 0 |
320 | #define CONFIG_SYS_OR4_PRELIM 0 | |
a562e1bd | 321 | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_BR5_PRELIM 0 |
323 | #define CONFIG_SYS_OR5_PRELIM 0 | |
a562e1bd | 324 | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_BR6_PRELIM 0 |
326 | #define CONFIG_SYS_OR6_PRELIM 0 | |
a562e1bd | 327 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_BR7_PRELIM 0x00000701 |
329 | #define CONFIG_SYS_OR7_PRELIM 0xFF00007C | |
a562e1bd WD |
330 | |
331 | /*----------------------------------------------------------------------- | |
332 | * LED config | |
333 | */ | |
334 | #define LED_STAT_0 0xffff /*all LEDs off*/ | |
335 | #define LED_STAT_1 0xfffe | |
336 | #define LED_STAT_2 0xfffd | |
337 | #define LED_STAT_3 0xfffb | |
338 | #define LED_STAT_4 0xfff7 | |
339 | #define LED_STAT_5 0xffef | |
340 | #define LED_STAT_6 0xffdf | |
341 | #define LED_STAT_7 0xff00 /*all LEDs on*/ | |
342 | ||
343 | /*----------------------------------------------------------------------- | |
344 | * Port configuration (GPIO) | |
345 | */ | |
6d0f6bcf | 346 | #define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external |
a562e1bd | 347 | GPIO*/ |
6d0f6bcf | 348 | #define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs |
a562e1bd | 349 | (1^=output, 0^=input) */ |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ |
351 | #define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART | |
a562e1bd | 352 | configuration */ |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ |
354 | #define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ | |
355 | #define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ | |
a562e1bd WD |
356 | |
357 | #endif /* _CONFIG_COBRA5272_H */ |