[people/ms/u-boot.git] / include / configs / cogent_mpc8260.h

/*
 * (C) Copyright 2000
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Config header file for Cogent platform using an MPC8xx CPU module
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/

/* Cogent Modular Architecture options */
#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
#define	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	66666666	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_KGDB

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

#ifdef DEBUG
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
# else
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# endif
#endif

#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Low Level Cogent settings
 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 * (second 2 for CMA120 only)
 */
#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */

#include <configs/cogent_common.h>

#ifdef CONFIG_CONS_NONE
#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
#endif
#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
#define CONFIG_SHOW_ACTIVITY

#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*
 * flash exists on the motherboard
 * set these four according to TOP dipsw:
 * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
 * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
 */
#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
#endif
#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
/* no slaves so just duplicate the master hrcw */
#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
#else
#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
#endif
#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
#else
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR		BCR_EBM

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR	0

#if defined(CONFIG_CMA282)

/*
 * Init Memory Controller:
 *
 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
 * and CS2 for (optional) local bus RAM on the CPU module.
 *
 * Note the motherboard address space (256 Mbyte in size) is connected
 * to the 60x Bus and is located starting at address 0. The Hard Reset
 * Configuration Word should put the 60x Bus into External Bus Mode, since
 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE	/* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
#if 0
#define CONFIG_SYS_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CONFIG_SYS_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)

/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif

#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0f8c9768 WD	6	*/
	7
	8	/*
	9	* Config header file for Cogent platform using an MPC8xx CPU module
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	21	#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
9c4c5ae3	22	#define CONFIG_CPM2 1 /* Has a CPM2 */
0f8c9768	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	25
c837dcb1	26	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
3a8f28d0	27	#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
c837dcb1	28
0f8c9768 WD	29	/* Cogent Modular Architecture options */
	30	#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
	31	#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
	32
	33	/*
	34	* select serial console configuration
	35	*
	36	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	37	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	38	* for SCC).
	39	*
	40	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	41	* defined elsewhere (for example, on the cogent platform, there are serial
	42	* ports on the motherboard which are used for the serial console - see
	43	* cogent/cma101/serial.[ch]).
	44	*/
	45	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	46	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	47	#undef CONFIG_CONS_NONE /* define if console on something else*/
	48	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	49	#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
	50	#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
	51	#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
	52
	53	/*
	54	* select ethernet configuration
	55	*
	56	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	57	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	58	* for FCC)
	59	*
	60	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	61	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
0f8c9768 WD	62	*/
	63	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	64	#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	65	#define CONFIG_ETHER_NONE /* define if ether on something else */
	66	#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
	67
	68	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	69	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	70
	71	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
	72	#define CONFIG_BAUDRATE 230400
	73	#else
	74	#define CONFIG_BAUDRATE 9600
	75	#endif
	76
0f8c9768	77
80ff4f99 JL	78	/*
	79	* BOOTP options
	80	*/
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82	#define CONFIG_BOOTP_BOOTPATH
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_HOSTNAME
	85
	86
37e4f24b JL	87	/*
	88	* Command line configuration.
	89	*/
	90	#include <config_cmd_default.h>
	91
	92	#define CONFIG_CMD_KGDB
	93
	94	#undef CONFIG_CMD_NET
ba273f06	95	#undef CONFIG_CMD_NFS
0f8c9768 WD	96
	97	#ifdef DEBUG
	98	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	99	#else
	100	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	101	#endif
	102	#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
	103
	104	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	105
37e4f24b	106	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	107	#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	108	#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	109	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	110	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	111	#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
	112	#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
	113	#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
	114	# if defined(CONFIG_KGDB_NONE) \|\| defined(CONFIG_KGDB_USE_EXTC)
	115	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
	116	# else
	117	#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
	118	# endif
	119	#endif
	120
	121	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	122
	123	/*
	124	* Miscellaneous configurable options
	125	*/
6d0f6bcf	126	#define CONFIG_SYS_LONGHELP /* undef to save memory */
37e4f24b	127	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	128	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	129	#else
6d0f6bcf	130	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	131	#endif
6d0f6bcf JCPV	132	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	133	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	134	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	137	#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
0f8c9768	138
6d0f6bcf	139	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	140
6d0f6bcf	141	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
0f8c9768 WD	142
	143	/*
	144	* Low Level Configuration Settings
	145	* (address mappings, register initial values, etc.)
	146	* You should know what you are doing if you make changes here.
	147	*/
	148
	149	/*-----------------------------------------------------------------------
	150	* Low Level Cogent settings
6d0f6bcf	151	* if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
0f8c9768 WD	152	* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
	153	* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
	154	* (second 2 for CMA120 only)
	155	*/
6d0f6bcf	156	#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
0f8c9768 WD	157
	158	#include <configs/cogent_common.h>
	159
	160	#ifdef CONFIG_CONS_NONE
6d0f6bcf	161	#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
0f8c9768	162	#endif
6d0f6bcf	163	#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
a8c7c708	164	#define CONFIG_SHOW_ACTIVITY
0f8c9768 WD	165
	166	#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
	167	/*
	168	* flash exists on the motherboard
	169	* set these four according to TOP dipsw:
	170	* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
	171	* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
	172	*/
	173	#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
	174	#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
	175	#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
	176	#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
	177	#endif
	178	#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
	179	#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
	180
	181	/*-----------------------------------------------------------------------
	182	* Hard Reset Configuration Words
	183	*
6d0f6bcf	184	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
0f8c9768	185	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	186	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
0f8c9768	187	*/
6d0f6bcf	188	#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM\|HRCW_BPS10\|HRCW_L2CPC10\|HRCW_DPPC11\|\
0f8c9768 WD	189	HRCW_ISB100\|HRCW_MMR11\|HRCW_MODCK_H0101)
0f8c9768 WD	190	/* no slaves so just duplicate the master hrcw */
6d0f6bcf JCPV	191	#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
	192	#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
	193	#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
	194	#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
	195	#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
	196	#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
	197	#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
0f8c9768 WD	198
	199	/*-----------------------------------------------------------------------
	200	* Internal Memory Mapped Register
	201	*/
6d0f6bcf	202	#define CONFIG_SYS_IMMR 0xF0000000
0f8c9768 WD	203
	204	/*-----------------------------------------------------------------------
	205	* Definitions for initial stack pointer and data area (in DPRAM)
	206	*/
6d0f6bcf	207	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	208	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	209	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	210	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	211
	212	/*-----------------------------------------------------------------------
	213	* Start addresses for the final memory configuration
	214	* (Set up by the startup code)
6d0f6bcf	215	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	216	*/
6d0f6bcf	217	#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
0f8c9768	218	#ifdef CONFIG_CMA302
6d0f6bcf	219	#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
0f8c9768	220	#else
6d0f6bcf	221	#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
0f8c9768	222	#endif
14d0a02a	223	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	224	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	225	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
0f8c9768 WD	226
	227	/*
	228	* For booting Linux, the board info and command line data
	229	* have to be in the first 8 MB of memory, since this is
	230	* the maximum mapped by the Linux kernel during initialization.
	231	*/
6d0f6bcf	232	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
0f8c9768 WD	233
	234	/*-----------------------------------------------------------------------
	235	* FLASH organization
	236	*/
6d0f6bcf JCPV	237	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
6d0f6bcf JCPV	238	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
0f8c9768	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	241	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
0f8c9768	242
5a1aceb0	243	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	244	#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
0f8c9768	245	#ifdef CONFIG_CMA302
0e8d1586 JCPV	246	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0e8d1586 JCPV	247	#define CONFIG_ENV_SECT_SIZE (5121024) / see README - env sect real size */
0f8c9768	248	#else
0e8d1586	249	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
0f8c9768 WD	250	#endif
	251
	252	/*-----------------------------------------------------------------------
	253	* Cache Configuration
	254	*/
6d0f6bcf	255	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
37e4f24b	256	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	257	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
0f8c9768 WD	258	#endif
	259
	260	/*-----------------------------------------------------------------------
	261	* HIDx - Hardware Implementation-dependent Registers 2-11
	262	*-----------------------------------------------------------------------
	263	* HID0 also contains cache control - initially enable both caches and
	264	* invalidate contents, then the final state leaves only the instruction
	265	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	266	* but Soft reset does not.
	267	*
	268	* HID1 has only read-only information - nothing to set.
	269	*/
6d0f6bcf	270	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
0f8c9768	271	HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	272	#define CONFIG_SYS_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	273	#define CONFIG_SYS_HID2 0
0f8c9768 WD	274
	275	/*-----------------------------------------------------------------------
	276	* RMR - Reset Mode Register 5-5
	277	*-----------------------------------------------------------------------
	278	* turn on Checkstop Reset Enable
	279	*/
6d0f6bcf	280	#define CONFIG_SYS_RMR RMR_CSRE
0f8c9768 WD	281
	282	/*-----------------------------------------------------------------------
	283	* BCR - Bus Configuration 4-25
	284	*-----------------------------------------------------------------------
	285	*/
6d0f6bcf	286	#define CONFIG_SYS_BCR BCR_EBM
0f8c9768 WD	287
	288	/*-----------------------------------------------------------------------
	289	* SIUMCR - SIU Module Configuration 4-31
	290	*-----------------------------------------------------------------------
	291	*/
6d0f6bcf	292	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11\|SIUMCR_L2CPC10\|SIUMCR_MMR11)
0f8c9768 WD	293
	294	/*-----------------------------------------------------------------------
	295	* SYPCR - System Protection Control 4-35
	296	* SYPCR can only be written once after reset!
	297	*-----------------------------------------------------------------------
	298	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	299	*/
	300	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	301	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
0f8c9768 WD	302	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
0f8c9768 WD	303	#else
6d0f6bcf	304	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
0f8c9768 WD	305	SYPCR_SWRI\|SYPCR_SWP)
	306	#endif /* CONFIG_WATCHDOG */
	307
	308	/*-----------------------------------------------------------------------
	309	* TMCNTSC - Time Counter Status and Control 4-40
	310	*-----------------------------------------------------------------------
	311	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	312	* and enable Time Counter
	313	*/
6d0f6bcf	314	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
0f8c9768 WD	315
	316	/*-----------------------------------------------------------------------
	317	* PISCR - Periodic Interrupt Status and Control 4-42
	318	*-----------------------------------------------------------------------
	319	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	320	* Periodic timer
	321	*/
6d0f6bcf	322	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
0f8c9768 WD	323
	324	/*-----------------------------------------------------------------------
	325	* SCCR - System Clock Control 9-8
	326	*-----------------------------------------------------------------------
	327	* Ensure DFBRG is Divide by 16
	328	*/
6d0f6bcf	329	#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
0f8c9768 WD	330
	331	/*-----------------------------------------------------------------------
	332	* RCCR - RISC Controller Configuration 13-7
	333	*-----------------------------------------------------------------------
	334	*/
6d0f6bcf	335	#define CONFIG_SYS_RCCR 0
0f8c9768 WD	336
	337	#if defined(CONFIG_CMA282)
	338
	339	/*
	340	* Init Memory Controller:
	341	*
	342	* According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
	343	* and CS2 for (optional) local bus RAM on the CPU module.
	344	*
	345	* Note the motherboard address space (256 Mbyte in size) is connected
	346	* to the 60x Bus and is located starting at address 0. The Hard Reset
	347	* Configuration Word should put the 60x Bus into External Bus Mode, since
	348	* we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
	349	*
	350	* (the *_SIZE vars must be a power of 2)
	351	*/
	352
14d0a02a	353	#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
6d0f6bcf	354	#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
0f8c9768	355	#if 0
6d0f6bcf JCPV	356	#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
6d0f6bcf JCPV	357	#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
0f8c9768 WD	358	#endif
	359
	360	/*
	361	* CS0 maps the EPROM on the cpu module
6d0f6bcf	362	* Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
0f8c9768 WD	363	*
	364	* Note: We must have already transferred control to the final location
	365	* of the EPROM before these are used, because when BR0/OR0 are set, the
	366	* mirror of the eprom at any other addresses will disappear.
	367	*/
	368
6d0f6bcf JCPV	369	/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
	370	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)\|BRx_PS_16\|BRx_WP\|BRx_V)
	371	/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
	372	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)\|\
0f8c9768 WD	373	ORxG_CSNT\|ORxG_ACS_DIV2\|ORxG_SCY_10_CLK)
	374
	375	/*
	376	* CS2 enables the Local Bus SDRAM on the CPU Module
	377	*
	378	* Will leave this unset for the moment, because a) my CPU module has no
	379	* SDRAM installed (it is optional); and b) it will require programming
	380	* one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
	381	* if you can't test it.
	382	*/
	383
	384	#if 0
6d0f6bcf JCPV	385	/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
	386	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)\|BRx_PS_32\|/???/\|BRx_V)
	387	/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
	388	#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)\|/???/)
0f8c9768 WD	389	#endif
	390
	391	#endif
0f8c9768	392	#endif /* __CONFIG_H */