[people/ms/u-boot.git] / include / configs / cogent_mpc8260.h

/*
 * (C) Copyright 2000
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Config header file for Cogent platform using an MPC8xx CPU module
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/

/* Cogent Modular Architecture options */
#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
#define	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	66666666	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_KGDB

#undef CONFIG_CMD_NET


#ifdef DEBUG
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
# else
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# endif
#endif

#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Low Level Cogent settings
 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 * (second 2 for CMA120 only)
 */
#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */

#include <configs/cogent_common.h>

#ifdef CONFIG_CONS_NONE
#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
#endif
#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
#define CONFIG_SHOW_ACTIVITY

#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*
 * flash exists on the motherboard
 * set these four according to TOP dipsw:
 * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
 * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
 */
#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
#endif
#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
/* no slaves so just duplicate the master hrcw */
#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
#else
#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
#endif
#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
#else
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR		BCR_EBM

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR	0

#if defined(CONFIG_CMA282)

/*
 * Init Memory Controller:
 *
 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
 * and CS2 for (optional) local bus RAM on the CPU module.
 *
 * Note the motherboard address space (256 Mbyte in size) is connected
 * to the 60x Bus and is located starting at address 0. The Hard Reset
 * Configuration Word should put the 60x Bus into External Bus Mode, since
 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CONFIG_SYS_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
#if 0
#define CONFIG_SYS_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CONFIG_SYS_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)

/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif

#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Config header file for Cogent platform using an MPC8xx CPU module
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	37	#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
9c4c5ae3	38	#define CONFIG_CPM2 1 /* Has a CPM2 */
0f8c9768	39
c837dcb1 WD	40	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
c837dcb1 WD	41
0f8c9768 WD	42	/* Cogent Modular Architecture options */
	43	#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
	44	#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
	45
	46	/*
	47	* select serial console configuration
	48	*
	49	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	50	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	51	* for SCC).
	52	*
	53	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	54	* defined elsewhere (for example, on the cogent platform, there are serial
	55	* ports on the motherboard which are used for the serial console - see
	56	* cogent/cma101/serial.[ch]).
	57	*/
	58	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	59	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	60	#undef CONFIG_CONS_NONE /* define if console on something else*/
	61	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	62	#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
	63	#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
	64	#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
	65
	66	/*
	67	* select ethernet configuration
	68	*
	69	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	70	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	71	* for FCC)
	72	*
	73	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	74	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
0f8c9768 WD	75	*/
	76	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	77	#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	78	#define CONFIG_ETHER_NONE /* define if ether on something else */
	79	#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
	80
	81	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	82	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	83
	84	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
	85	#define CONFIG_BAUDRATE 230400
	86	#else
	87	#define CONFIG_BAUDRATE 9600
	88	#endif
	89
0f8c9768	90
80ff4f99 JL	91	/*
	92	* BOOTP options
	93	*/
	94	#define CONFIG_BOOTP_BOOTFILESIZE
	95	#define CONFIG_BOOTP_BOOTPATH
	96	#define CONFIG_BOOTP_GATEWAY
	97	#define CONFIG_BOOTP_HOSTNAME
	98
	99
37e4f24b JL	100	/*
	101	* Command line configuration.
	102	*/
	103	#include <config_cmd_default.h>
	104
	105	#define CONFIG_CMD_KGDB
	106
	107	#undef CONFIG_CMD_NET
	108
0f8c9768 WD	109
	110	#ifdef DEBUG
	111	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	112	#else
	113	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	114	#endif
	115	#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
	116
	117	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	118
37e4f24b	119	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	120	#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	121	#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	122	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	123	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	124	#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
	125	#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
	126	#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
	127	# if defined(CONFIG_KGDB_NONE) \|\| defined(CONFIG_KGDB_USE_EXTC)
	128	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
	129	# else
	130	#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
	131	# endif
	132	#endif
	133
	134	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
	135
	136	/*
	137	* Miscellaneous configurable options
	138	*/
6d0f6bcf JCPV	139	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	140	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
37e4f24b	141	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	142	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	143	#else
6d0f6bcf	144	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	145	#endif
6d0f6bcf JCPV	146	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	147	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	148	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	149
6d0f6bcf JCPV	150	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	151	#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
0f8c9768	152
6d0f6bcf	153	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	154
6d0f6bcf	155	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	156
6d0f6bcf	157	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
0f8c9768 WD	158
	159	/*
	160	* Low Level Configuration Settings
	161	* (address mappings, register initial values, etc.)
	162	* You should know what you are doing if you make changes here.
	163	*/
	164
	165	/*-----------------------------------------------------------------------
	166	* Low Level Cogent settings
6d0f6bcf	167	* if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
0f8c9768 WD	168	* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
	169	* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
	170	* (second 2 for CMA120 only)
	171	*/
6d0f6bcf	172	#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
0f8c9768 WD	173
	174	#include <configs/cogent_common.h>
	175
	176	#ifdef CONFIG_CONS_NONE
6d0f6bcf	177	#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
0f8c9768	178	#endif
6d0f6bcf	179	#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
a8c7c708	180	#define CONFIG_SHOW_ACTIVITY
0f8c9768 WD	181
	182	#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
	183	/*
	184	* flash exists on the motherboard
	185	* set these four according to TOP dipsw:
	186	* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
	187	* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
	188	*/
	189	#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
	190	#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
	191	#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
	192	#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
	193	#endif
	194	#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
	195	#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
	196
	197	/*-----------------------------------------------------------------------
	198	* Hard Reset Configuration Words
	199	*
6d0f6bcf	200	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
0f8c9768	201	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	202	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
0f8c9768	203	*/
6d0f6bcf	204	#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM\|HRCW_BPS10\|HRCW_L2CPC10\|HRCW_DPPC11\|\
0f8c9768 WD	205	HRCW_ISB100\|HRCW_MMR11\|HRCW_MODCK_H0101)
0f8c9768 WD	206	/* no slaves so just duplicate the master hrcw */
6d0f6bcf JCPV	207	#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
	208	#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
	209	#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
	210	#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
	211	#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
	212	#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
	213	#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
0f8c9768 WD	214
	215	/*-----------------------------------------------------------------------
	216	* Internal Memory Mapped Register
	217	*/
6d0f6bcf	218	#define CONFIG_SYS_IMMR 0xF0000000
0f8c9768 WD	219
	220	/*-----------------------------------------------------------------------
	221	* Definitions for initial stack pointer and data area (in DPRAM)
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	224	#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
	225	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	226	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	227	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	228
	229	/*-----------------------------------------------------------------------
	230	* Start addresses for the final memory configuration
	231	* (Set up by the startup code)
6d0f6bcf	232	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	233	*/
6d0f6bcf	234	#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
0f8c9768	235	#ifdef CONFIG_CMA302
6d0f6bcf	236	#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
0f8c9768	237	#else
6d0f6bcf	238	#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
0f8c9768	239	#endif
6d0f6bcf JCPV	240	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	241	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	242	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
0f8c9768 WD	243
	244	/*
	245	* For booting Linux, the board info and command line data
	246	* have to be in the first 8 MB of memory, since this is
	247	* the maximum mapped by the Linux kernel during initialization.
	248	*/
6d0f6bcf	249	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
0f8c9768 WD	250
	251	/*-----------------------------------------------------------------------
	252	* FLASH organization
	253	*/
6d0f6bcf JCPV	254	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
6d0f6bcf JCPV	255	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
0f8c9768	256
6d0f6bcf JCPV	257	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	258	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
0f8c9768	259
5a1aceb0	260	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	261	#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
0f8c9768	262	#ifdef CONFIG_CMA302
0e8d1586 JCPV	263	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0e8d1586 JCPV	264	#define CONFIG_ENV_SECT_SIZE (5121024) / see README - env sect real size */
0f8c9768	265	#else
0e8d1586	266	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
0f8c9768 WD	267	#endif
	268
	269	/*-----------------------------------------------------------------------
	270	* Cache Configuration
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
37e4f24b	273	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	274	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
0f8c9768 WD	275	#endif
	276
	277	/*-----------------------------------------------------------------------
	278	* HIDx - Hardware Implementation-dependent Registers 2-11
	279	*-----------------------------------------------------------------------
	280	* HID0 also contains cache control - initially enable both caches and
	281	* invalidate contents, then the final state leaves only the instruction
	282	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	283	* but Soft reset does not.
	284	*
	285	* HID1 has only read-only information - nothing to set.
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
0f8c9768	288	HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	289	#define CONFIG_SYS_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	290	#define CONFIG_SYS_HID2 0
0f8c9768 WD	291
	292	/*-----------------------------------------------------------------------
	293	* RMR - Reset Mode Register 5-5
	294	*-----------------------------------------------------------------------
	295	* turn on Checkstop Reset Enable
	296	*/
6d0f6bcf	297	#define CONFIG_SYS_RMR RMR_CSRE
0f8c9768 WD	298
	299	/*-----------------------------------------------------------------------
	300	* BCR - Bus Configuration 4-25
	301	*-----------------------------------------------------------------------
	302	*/
6d0f6bcf	303	#define CONFIG_SYS_BCR BCR_EBM
0f8c9768 WD	304
	305	/*-----------------------------------------------------------------------
	306	* SIUMCR - SIU Module Configuration 4-31
	307	*-----------------------------------------------------------------------
	308	*/
6d0f6bcf	309	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11\|SIUMCR_L2CPC10\|SIUMCR_MMR11)
0f8c9768 WD	310
	311	/*-----------------------------------------------------------------------
	312	* SYPCR - System Protection Control 4-35
	313	* SYPCR can only be written once after reset!
	314	*-----------------------------------------------------------------------
	315	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	316	*/
	317	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	318	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
0f8c9768 WD	319	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
0f8c9768 WD	320	#else
6d0f6bcf	321	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
0f8c9768 WD	322	SYPCR_SWRI\|SYPCR_SWP)
	323	#endif /* CONFIG_WATCHDOG */
	324
	325	/*-----------------------------------------------------------------------
	326	* TMCNTSC - Time Counter Status and Control 4-40
	327	*-----------------------------------------------------------------------
	328	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	329	* and enable Time Counter
	330	*/
6d0f6bcf	331	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
0f8c9768 WD	332
	333	/*-----------------------------------------------------------------------
	334	* PISCR - Periodic Interrupt Status and Control 4-42
	335	*-----------------------------------------------------------------------
	336	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	337	* Periodic timer
	338	*/
6d0f6bcf	339	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
0f8c9768 WD	340
	341	/*-----------------------------------------------------------------------
	342	* SCCR - System Clock Control 9-8
	343	*-----------------------------------------------------------------------
	344	* Ensure DFBRG is Divide by 16
	345	*/
6d0f6bcf	346	#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
0f8c9768 WD	347
	348	/*-----------------------------------------------------------------------
	349	* RCCR - RISC Controller Configuration 13-7
	350	*-----------------------------------------------------------------------
	351	*/
6d0f6bcf	352	#define CONFIG_SYS_RCCR 0
0f8c9768 WD	353
	354	#if defined(CONFIG_CMA282)
	355
	356	/*
	357	* Init Memory Controller:
	358	*
	359	* According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
	360	* and CS2 for (optional) local bus RAM on the CPU module.
	361	*
	362	* Note the motherboard address space (256 Mbyte in size) is connected
	363	* to the 60x Bus and is located starting at address 0. The Hard Reset
	364	* Configuration Word should put the 60x Bus into External Bus Mode, since
	365	* we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
	366	*
	367	* (the *_SIZE vars must be a power of 2)
	368	*/
	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */
6d0f6bcf JCPV	371	#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
0f8c9768	372	#if 0
6d0f6bcf JCPV	373	#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
6d0f6bcf JCPV	374	#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
0f8c9768 WD	375	#endif
	376
	377	/*
	378	* CS0 maps the EPROM on the cpu module
6d0f6bcf	379	* Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
0f8c9768 WD	380	*
	381	* Note: We must have already transferred control to the final location
	382	* of the EPROM before these are used, because when BR0/OR0 are set, the
	383	* mirror of the eprom at any other addresses will disappear.
	384	*/
	385
6d0f6bcf JCPV	386	/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
	387	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)\|BRx_PS_16\|BRx_WP\|BRx_V)
	388	/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
	389	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)\|\
0f8c9768 WD	390	ORxG_CSNT\|ORxG_ACS_DIV2\|ORxG_SCY_10_CLK)
	391
	392	/*
	393	* CS2 enables the Local Bus SDRAM on the CPU Module
	394	*
	395	* Will leave this unset for the moment, because a) my CPU module has no
	396	* SDRAM installed (it is optional); and b) it will require programming
	397	* one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
	398	* if you can't test it.
	399	*/
	400
	401	#if 0
6d0f6bcf JCPV	402	/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
	403	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)\|BRx_PS_32\|/???/\|BRx_V)
	404	/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
	405	#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)\|/???/)
0f8c9768 WD	406	#endif
	407
	408	#endif
	409
	410	/*
	411	* Internal Definitions
	412	*
	413	* Boot Flags
	414	*/
	415	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
	416	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	417
	418	#endif /* __CONFIG_H */