[people/ms/u-boot.git] / include / configs / cogent_mpc8260.h

/*
 * (C) Copyright 2000
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Config header file for Cogent platform using an MPC8xx CPU module
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */

/* Cogent Modular Architecture options */
#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
#define	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	66666666	/* in Hz */

#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE		230400
#else
#define CONFIG_BAUDRATE		9600
#endif

#define CONFIG_COMMANDS		((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#ifdef DEBUG
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
# else
#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
# endif
#endif

#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Low Level Cogent settings
 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 * (second 2 for CMA120 only)
 */
#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */

#include <configs/cogent_common.h>

#ifdef CONFIG_CONS_NONE
#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
#endif
#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */

#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*
 * flash exists on the motherboard
 * set these four according to TOP dipsw:
 * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
 * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
 */
#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
#endif
#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#define CFG_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
/* no slaves so just duplicate the master hrcw */
#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
#else
#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
#endif
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
#else
#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
				HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CFG_BCR		BCR_EBM

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CFG_SCCR	(SCCR_DFBRG01)

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR	0

#if defined(CONFIG_CMA282)

/*
 * Init Memory Controller:
 *
 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
 * and CS2 for (optional) local bus RAM on the CPU module.
 *
 * Note the motherboard address space (256 Mbyte in size) is connected
 * to the 60x Bus and is located starting at address 0. The Hard Reset
 * Configuration Word should put the 60x Bus into External Bus Mode, since
 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
#define CFG_CMA_CS0_SIZE	(1 << 20)
#if 0
#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
#define CFG_CMA_CS2_SIZE	(16 << 20)
#endif

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)

/*
 * CS2 enables the Local Bus SDRAM on the CPU Module
 *
 * Will leave this unset for the moment, because a) my CPU module has no
 * SDRAM installed (it is optional); and b) it will require programming
 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
 * if you can't test it.
 */

#if 0
/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
#endif

#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Config header file for Cogent platform using an MPC8xx CPU module
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	37	#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
	38
	39	/* Cogent Modular Architecture options */
	40	#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
	41	#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
	42
	43	/*
	44	* select serial console configuration
	45	*
	46	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	47	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	48	* for SCC).
	49	*
	50	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	51	* defined elsewhere (for example, on the cogent platform, there are serial
	52	* ports on the motherboard which are used for the serial console - see
	53	* cogent/cma101/serial.[ch]).
	54	*/
	55	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	56	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	57	#undef CONFIG_CONS_NONE /* define if console on something else*/
	58	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	59	#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
	60	#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
	61	#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
	62
	63	/*
	64	* select ethernet configuration
65	*
66	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
68	* for FCC)
69	*
70	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
71	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
72	* from CONFIG_COMMANDS to remove support for networking.
73	*/
74	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75	#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76	#define CONFIG_ETHER_NONE /* define if ether on something else */
77	#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
78
79	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
80	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
81
82	#if defined(CONFIG_CONS_NONE) \|\| defined(CONFIG_CONS_USE_EXTC)
83	#define CONFIG_BAUDRATE 230400
84	#else
85	#define CONFIG_BAUDRATE 9600
86	#endif
87
88	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL\|CFG_CMD_KGDB)&~CFG_CMD_NET)
89
90	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91	#include <cmd_confdefs.h>
92
93	#ifdef DEBUG
94	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
95	#else
96	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
97	#endif
98	#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
99
100	#define CONFIG_BOOTARGS "root=/dev/ram rw"
101
102	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
103	#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
104	#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
105	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
106	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
107	#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
108	#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
109	#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
110	# if defined(CONFIG_KGDB_NONE) \|\| defined(CONFIG_KGDB_USE_EXTC)
111	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
112	# else
113	#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
114	# endif
115	#endif
116
117	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
118
119	/*
120	* Miscellaneous configurable options
121	*/
122	#define CFG_LONGHELP /* undef to save memory */
123	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
124	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
125	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
126	#else
127	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
128	#endif
129	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
130	#define CFG_MAXARGS 16 /* max number of command args */
131	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
132
133	#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
134	#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
135
136	#define CFG_LOAD_ADDR 0x100000 /* default load address */
137
138	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
139
140	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
141
142	/*
143	* Low Level Configuration Settings
144	* (address mappings, register initial values, etc.)
145	* You should know what you are doing if you make changes here.
146	*/
147
148	/*-----------------------------------------------------------------------
149	* Low Level Cogent settings
150	* if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
151	* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
152	* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
153	* (second 2 for CMA120 only)
154	*/
155	#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
156
157	#include <configs/cogent_common.h>
158
159	#ifdef CONFIG_CONS_NONE
160	#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
161	#endif
162	#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
163
164	#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
165	/*
166	* flash exists on the motherboard
167	* set these four according to TOP dipsw:
168	* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
169	* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
170	*/
171	#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
172	#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
173	#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
174	#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
175	#endif
176	#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
177	#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
178
179	/*-----------------------------------------------------------------------
180	* Hard Reset Configuration Words
181	*
182	* if you change bits in the HRCW, you must also change the CFG_*
183	* defines for the various registers affected by the HRCW e.g. changing
184	* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
185	*/
186	#define CFG_HRCW_MASTER (HRCW_EBM\|HRCW_BPS10\|HRCW_L2CPC10\|HRCW_DPPC11\|\
187	HRCW_ISB100\|HRCW_MMR11\|HRCW_MODCK_H0101)
188	/* no slaves so just duplicate the master hrcw */
189	#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
190	#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
191	#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
192	#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
193	#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
194	#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
195	#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
196
197	/*-----------------------------------------------------------------------
198	* Internal Memory Mapped Register
199	*/
200	#define CFG_IMMR 0xF0000000
201
202	/*-----------------------------------------------------------------------
203	* Definitions for initial stack pointer and data area (in DPRAM)
204	*/
205	#define CFG_INIT_RAM_ADDR CFG_IMMR
206	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
207	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
208	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
209	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
210
211	/*-----------------------------------------------------------------------
212	* Start addresses for the final memory configuration
213	* (Set up by the startup code)
214	* Please note that CFG_SDRAM_BASE _must_ start at 0
215	*/
216	#define CFG_SDRAM_BASE CMA_MB_RAM_BASE
217	#ifdef CONFIG_CMA302
218	#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
219	#else
220	#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
221	#endif
222	#define CFG_MONITOR_BASE TEXT_BASE
223	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
224	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
225
226	/*
227	* For booting Linux, the board info and command line data
228	* have to be in the first 8 MB of memory, since this is
229	* the maximum mapped by the Linux kernel during initialization.
230	*/
231	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
232
233	/*-----------------------------------------------------------------------
234	* FLASH organization
235	*/
236	#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
237	#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
238
239	#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
240	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
241
242	#define CFG_ENV_IS_IN_FLASH 1
243	#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
244	#ifdef CONFIG_CMA302
245	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
246	#define CFG_ENV_SECT_SIZE (5121024) / see README - env sect real size */
247	#else
248	#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
249	#endif
250
251	/*-----------------------------------------------------------------------
252	* Cache Configuration
253	*/
254	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
255	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
256	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
257	#endif
258
259	/*-----------------------------------------------------------------------
260	* HIDx - Hardware Implementation-dependent Registers 2-11
261	*-----------------------------------------------------------------------
262	* HID0 also contains cache control - initially enable both caches and
263	* invalidate contents, then the final state leaves only the instruction
264	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
265	* but Soft reset does not.
266	*
267	* HID1 has only read-only information - nothing to set.
268	*/
269	#define CFG_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|\
270	HID0_IFEM\|HID0_ABE)
271	#define CFG_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE)
272	#define CFG_HID2 0
273
274	/*-----------------------------------------------------------------------
275	* RMR - Reset Mode Register 5-5
276	*-----------------------------------------------------------------------
277	* turn on Checkstop Reset Enable
278	*/
279	#define CFG_RMR RMR_CSRE
280
281	/*-----------------------------------------------------------------------
282	* BCR - Bus Configuration 4-25
283	*-----------------------------------------------------------------------
284	*/
285	#define CFG_BCR BCR_EBM
286
287	/*-----------------------------------------------------------------------
288	* SIUMCR - SIU Module Configuration 4-31
289	*-----------------------------------------------------------------------
290	*/
291	#define CFG_SIUMCR (SIUMCR_DPPC11\|SIUMCR_L2CPC10\|SIUMCR_MMR11)
292
293	/*-----------------------------------------------------------------------
294	* SYPCR - System Protection Control 4-35
295	* SYPCR can only be written once after reset!
296	*-----------------------------------------------------------------------
297	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
298	*/
299	#if defined(CONFIG_WATCHDOG)
300	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
301	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
302	#else
303	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
304	SYPCR_SWRI\|SYPCR_SWP)
305	#endif /* CONFIG_WATCHDOG */
306
307	/*-----------------------------------------------------------------------
308	* TMCNTSC - Time Counter Status and Control 4-40
309	*-----------------------------------------------------------------------
310	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
311	* and enable Time Counter
312	*/
313	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
314
315	/*-----------------------------------------------------------------------
316	* PISCR - Periodic Interrupt Status and Control 4-42
317	*-----------------------------------------------------------------------
318	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
319	* Periodic timer
320	*/
321	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
322
323	/*-----------------------------------------------------------------------
324	* SCCR - System Clock Control 9-8
325	*-----------------------------------------------------------------------
326	* Ensure DFBRG is Divide by 16
327	*/
328	#define CFG_SCCR (SCCR_DFBRG01)
329
330	/*-----------------------------------------------------------------------
331	* RCCR - RISC Controller Configuration 13-7
332	*-----------------------------------------------------------------------
333	*/
334	#define CFG_RCCR 0
335
336	#if defined(CONFIG_CMA282)
337
338	/*
339	* Init Memory Controller:
340	*
341	* According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
342	* and CS2 for (optional) local bus RAM on the CPU module.
343	*
344	* Note the motherboard address space (256 Mbyte in size) is connected
345	* to the 60x Bus and is located starting at address 0. The Hard Reset
346	* Configuration Word should put the 60x Bus into External Bus Mode, since
347	* we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
348	*
349	* (the *_SIZE vars must be a power of 2)
350	*/
351
352	#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
353	#define CFG_CMA_CS0_SIZE (1 << 20)
354	#if 0
355	#define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
356	#define CFG_CMA_CS2_SIZE (16 << 20)
357	#endif
358
359	/*
360	* CS0 maps the EPROM on the cpu module
361	* Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
362	*
363	* Note: We must have already transferred control to the final location
364	* of the EPROM before these are used, because when BR0/OR0 are set, the
365	* mirror of the eprom at any other addresses will disappear.
366	*/
367
368	/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
369	#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)\|BRx_PS_16\|BRx_WP\|BRx_V)
370	/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
371	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)\|\
372	ORxG_CSNT\|ORxG_ACS_DIV2\|ORxG_SCY_10_CLK)
373
374	/*
375	* CS2 enables the Local Bus SDRAM on the CPU Module
376	*
377	* Will leave this unset for the moment, because a) my CPU module has no
378	* SDRAM installed (it is optional); and b) it will require programming
379	* one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
380	* if you can't test it.
381	*/
382
383	#if 0
384	/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
385	#define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)\|BRx_PS_32\|/???/\|BRx_V)
386	/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
387	#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)\|/???/)
388	#endif
389
390	#endif
391
392	/*
393	* Internal Definitions
394	*
395	* Boot Flags
396	*/
397	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
398	#define BOOTFLAG_WARM 0x02 /* Software reboot */
399
400	#endif /* __CONFIG_H */