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ae440ab0 SA |
1 | /* |
2 | * Copyright 2016 Toradex AG | |
3 | * | |
4 | * Configuration settings for the Colibri iMX7 module. | |
5 | * | |
6 | * based on mx7dsabresd.h: | |
7 | * Copyright (C) 2015 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __COLIBRI_IMX7_CONFIG_H | |
13 | #define __COLIBRI_IMX7_CONFIG_H | |
14 | ||
15 | #include "mx7_common.h" | |
16 | ||
ae440ab0 SA |
17 | /*#define CONFIG_DBG_MONITOR*/ |
18 | #define PHYS_SDRAM_SIZE SZ_512M | |
19 | ||
b891d010 MZ |
20 | #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ |
21 | ||
b891d010 | 22 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
ae440ab0 SA |
23 | |
24 | /* Size of malloc() pool */ | |
25 | #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) | |
26 | ||
ae440ab0 SA |
27 | /* Network */ |
28 | #define CONFIG_FEC_MXC | |
29 | #define CONFIG_MII | |
30 | #define CONFIG_FEC_XCV_TYPE RMII | |
31 | #define CONFIG_ETHPRIME "FEC" | |
32 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
33 | ||
ae440ab0 | 34 | #define CONFIG_IP_DEFRAG |
f7c81e28 MZ |
35 | #define CONFIG_TFTP_BLOCKSIZE 16352 |
36 | #define CONFIG_TFTP_TSIZE | |
ae440ab0 SA |
37 | |
38 | /* ENET1 */ | |
39 | #define IMX_FEC_BASE ENET_IPS_BASE_ADDR | |
40 | ||
41 | /* MMC Config*/ | |
42 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
43 | #define CONFIG_SYS_FSL_USDHC_NUM 1 | |
44 | ||
45 | #undef CONFIG_BOOTM_PLAN9 | |
46 | #undef CONFIG_BOOTM_RTEMS | |
47 | ||
48 | /* I2C configs */ | |
ae440ab0 | 49 | #define CONFIG_SYS_I2C_MXC |
ae440ab0 SA |
50 | #define CONFIG_SYS_I2C_SPEED 100000 |
51 | ||
52 | #define CONFIG_IPADDR 192.168.10.2 | |
53 | #define CONFIG_NETMASK 255.255.255.0 | |
54 | #define CONFIG_SERVERIP 192.168.10.1 | |
55 | ||
56 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
9af131e3 | 57 | "bootm_size=0x10000000\0" \ |
ae440ab0 SA |
58 | "fdt_addr_r=0x82000000\0" \ |
59 | "fdt_high=0xffffffff\0" \ | |
60 | "initrd_high=0xffffffff\0" \ | |
61 | "kernel_addr_r=0x81000000\0" \ | |
62 | "ramdisk_addr_r=0x82100000\0" | |
63 | ||
64 | #define SD_BOOTCMD \ | |
65 | "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ | |
66 | "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ | |
67 | "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ | |
68 | "run m4boot && " \ | |
69 | "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ | |
70 | "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ | |
71 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
72 | ||
73 | #define NFS_BOOTCMD \ | |
74 | "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ | |
75 | "nfsboot=run setup; " \ | |
76 | "setenv bootargs ${defargs} ${nfsargs} " \ | |
77 | "${setupargs} ${vidargs}; echo Booting from NFS...;" \ | |
78 | "dhcp ${kernel_addr_r} && " \ | |
79 | "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ | |
80 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
81 | ||
82 | #define UBI_BOOTCMD \ | |
83 | "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ | |
84 | "ubi.fm_autoconvert=1\0" \ | |
85 | "ubiboot=run setup; " \ | |
86 | "setenv bootargs ${defargs} ${ubiargs} " \ | |
87 | "${setupargs} ${vidargs}; echo Booting from NAND...; " \ | |
88 | "ubi part ubi && run m4boot && " \ | |
89 | "ubi read ${kernel_addr_r} kernel && " \ | |
90 | "ubi read ${fdt_addr_r} dtb && " \ | |
91 | "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
92 | ||
93 | #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" | |
94 | ||
95 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
96 | MEM_LAYOUT_ENV_SETTINGS \ | |
97 | NFS_BOOTCMD \ | |
98 | SD_BOOTCMD \ | |
99 | UBI_BOOTCMD \ | |
100 | "console=ttymxc0\0" \ | |
101 | "defargs=\0" \ | |
102 | "fdt_board=eval-v3\0" \ | |
103 | "fdt_fixup=;\0" \ | |
104 | "m4boot=;\0" \ | |
105 | "ip_dyn=yes\0" \ | |
106 | "kernel_file=zImage\0" \ | |
43ede0bc | 107 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
ae440ab0 SA |
108 | "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ |
109 | "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ | |
110 | "${board}/flash_eth.img && source ${loadaddr}\0" \ | |
111 | "setsdupdate=mmc rescan && setenv interface mmc && " \ | |
112 | "fatload ${interface} 0:1 ${loadaddr} " \ | |
113 | "${board}/flash_blk.img && source ${loadaddr}\0" \ | |
114 | "setup=setenv setupargs " \ | |
115 | "console=tty1 console=${console}" \ | |
64095704 | 116 | ",${baudrate}n8 ${memargs} consoleblank=0\0" \ |
ae440ab0 SA |
117 | "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ |
118 | "setusbupdate=usb start && setenv interface usb && " \ | |
119 | "fatload ${interface} 0:1 ${loadaddr} " \ | |
120 | "${board}/flash_blk.img && source ${loadaddr}\0" \ | |
121 | "splashpos=m,m\0" \ | |
122 | "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ | |
38045f54 | 123 | "updlevel=2\0" |
ae440ab0 SA |
124 | |
125 | /* Miscellaneous configurable options */ | |
ae440ab0 SA |
126 | |
127 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
128 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000) | |
129 | ||
130 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
131 | #define CONFIG_SYS_HZ 1000 | |
132 | ||
ae440ab0 SA |
133 | /* Physical Memory Map */ |
134 | #define CONFIG_NR_DRAM_BANKS 1 | |
135 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
136 | ||
137 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
138 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
139 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
140 | ||
141 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
142 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
143 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
144 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
145 | ||
e856bdcf | 146 | /* environment organization */ |
ae440ab0 SA |
147 | |
148 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
149 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ | |
150 | #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ | |
151 | #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ | |
152 | #define CONFIG_ENV_OFFSET (8 * SZ_64K) | |
153 | #elif defined(CONFIG_ENV_IS_IN_NAND) | |
ae440ab0 | 154 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
38045f54 | 155 | #define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) |
ae440ab0 SA |
156 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
157 | #endif | |
158 | ||
ae440ab0 SA |
159 | /* NAND stuff */ |
160 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
161 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
162 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
163 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
164 | #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES | |
ae440ab0 | 165 | |
ae440ab0 | 166 | /* Dynamic MTD partition support */ |
ae440ab0 SA |
167 | #define CONFIG_MTD_PARTITIONS |
168 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
ae440ab0 SA |
169 | |
170 | /* DMA stuff, needed for GPMI/MXS NAND support */ | |
ae440ab0 SA |
171 | |
172 | /* USB Configs */ | |
ae440ab0 SA |
173 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
174 | ||
175 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
176 | #define CONFIG_MXC_USB_FLAGS 0 | |
177 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 | |
178 | ||
179 | #define CONFIG_IMX_THERMAL | |
180 | ||
181 | #define CONFIG_USBD_HS | |
182 | ||
ae440ab0 | 183 | /* USB Device Firmware Update support */ |
ae440ab0 SA |
184 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M |
185 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
186 | ||
ae440ab0 | 187 | #ifdef CONFIG_VIDEO |
ae440ab0 SA |
188 | #define CONFIG_VIDEO_MXS |
189 | #define CONFIG_VIDEO_LOGO | |
ae440ab0 SA |
190 | #define CONFIG_SPLASH_SCREEN |
191 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
ae440ab0 SA |
192 | #define CONFIG_BMP_16BPP |
193 | #define CONFIG_VIDEO_BMP_RLE8 | |
194 | #define CONFIG_VIDEO_BMP_LOGO | |
195 | #endif | |
196 | ||
197 | #endif |