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2e49984b MV |
1 | /* |
2 | * Toradex Colibri PXA270 configuration file | |
3 | * | |
4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
2e49984b MV |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Board Configuration Options | |
14 | */ | |
abc20aba | 15 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
f9f5486c | 16 | #define CONFIG_SYS_TEXT_BASE 0x0 |
2e49984b | 17 | |
2e49984b MV |
18 | /* |
19 | * Environment settings | |
20 | */ | |
f9f5486c MV |
21 | #define CONFIG_ENV_OVERWRITE |
22 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) | |
23 | #define CONFIG_ARCH_CPU_INIT | |
2e49984b MV |
24 | #define CONFIG_BOOTCOMMAND \ |
25 | "if mmc init && fatload mmc 0 0xa0000000 uImage; then " \ | |
26 | "bootm 0xa0000000; " \ | |
27 | "fi; " \ | |
28 | "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ | |
29 | "bootm 0xa0000000; " \ | |
30 | "fi; " \ | |
31 | "bootm 0x80000;" | |
32 | #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" | |
33 | #define CONFIG_TIMESTAMP | |
34 | #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ | |
35 | #define CONFIG_CMDLINE_TAG | |
36 | #define CONFIG_SETUP_MEMORY_TAGS | |
2e49984b | 37 | #define CONFIG_LZMA /* LZMA compression support */ |
f9f5486c | 38 | #define CONFIG_OF_LIBFDT |
2e49984b MV |
39 | |
40 | /* | |
41 | * Serial Console Configuration | |
42 | */ | |
43 | #define CONFIG_PXA_SERIAL | |
44 | #define CONFIG_FFUART 1 | |
ce6971cd | 45 | #define CONFIG_CONS_INDEX 3 |
2e49984b | 46 | #define CONFIG_BAUDRATE 115200 |
2e49984b MV |
47 | |
48 | /* | |
49 | * Bootloader Components Configuration | |
50 | */ | |
51 | #include <config_cmd_default.h> | |
52 | ||
53 | #define CONFIG_CMD_NET | |
54 | #define CONFIG_CMD_ENV | |
55 | #undef CONFIG_CMD_IMLS | |
56 | #define CONFIG_CMD_MMC | |
57 | #define CONFIG_CMD_USB | |
58 | #define CONFIG_CMD_FLASH | |
59 | ||
60 | /* | |
61 | * Networking Configuration | |
62 | * chip on the Voipac PXA270 board | |
63 | */ | |
64 | #ifdef CONFIG_CMD_NET | |
65 | #define CONFIG_CMD_PING | |
66 | #define CONFIG_CMD_DHCP | |
67 | ||
2e49984b MV |
68 | #define CONFIG_DRIVER_DM9000 1 |
69 | #define CONFIG_DM9000_BASE 0x08000000 | |
70 | #define DM9000_IO (CONFIG_DM9000_BASE) | |
71 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
72 | #define CONFIG_NET_RETRY_COUNT 10 | |
73 | ||
74 | #define CONFIG_BOOTP_BOOTFILESIZE | |
75 | #define CONFIG_BOOTP_BOOTPATH | |
76 | #define CONFIG_BOOTP_GATEWAY | |
77 | #define CONFIG_BOOTP_HOSTNAME | |
78 | #endif | |
79 | ||
2e49984b MV |
80 | /* |
81 | * HUSH Shell Configuration | |
82 | */ | |
83 | #define CONFIG_SYS_HUSH_PARSER 1 | |
2e49984b | 84 | |
f9f5486c | 85 | #define CONFIG_SYS_LONGHELP |
2e49984b | 86 | #ifdef CONFIG_SYS_HUSH_PARSER |
f9f5486c | 87 | #define CONFIG_SYS_PROMPT "$ " |
2e49984b | 88 | #else |
f9f5486c | 89 | #define CONFIG_SYS_PROMPT "=> " |
2e49984b | 90 | #endif |
f9f5486c MV |
91 | #define CONFIG_SYS_CBSIZE 256 |
92 | #define CONFIG_SYS_PBSIZE \ | |
93 | (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
94 | #define CONFIG_SYS_MAXARGS 16 | |
95 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
2e49984b | 96 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
f9f5486c MV |
97 | #define CONFIG_CMDLINE_EDITING 1 |
98 | #define CONFIG_AUTO_COMPLETE 1 | |
99 | ||
2e49984b MV |
100 | |
101 | /* | |
102 | * Clock Configuration | |
103 | */ | |
f9f5486c MV |
104 | #define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ |
105 | #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ | |
2e49984b | 106 | |
2e49984b MV |
107 | /* |
108 | * DRAM Map | |
109 | */ | |
110 | #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ | |
111 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
112 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
113 | ||
114 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | |
115 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ | |
116 | ||
117 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | |
118 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
119 | ||
f9f5486c | 120 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 |
6ef6eb91 | 121 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
f9f5486c | 122 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
6ef6eb91 | 123 | |
2e49984b MV |
124 | /* |
125 | * NOR FLASH | |
126 | */ | |
127 | #ifdef CONFIG_CMD_FLASH | |
128 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
129 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
130 | ||
131 | #define CONFIG_SYS_FLASH_CFI | |
132 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
133 | ||
134 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) | |
135 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
136 | ||
f9f5486c MV |
137 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) |
138 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) | |
2e49984b MV |
139 | |
140 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
141 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
142 | ||
143 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
144 | ||
145 | #else /* No flash */ | |
146 | #define CONFIG_SYS_NO_FLASH | |
147 | #define CONFIG_SYS_ENV_IS_NOWHERE | |
148 | #endif | |
149 | ||
f9f5486c MV |
150 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
151 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
2e49984b | 152 | |
f9f5486c MV |
153 | #define CONFIG_ENV_ADDR \ |
154 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
155 | #define CONFIG_ENV_SIZE 0x40000 | |
156 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
157 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
158 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
2e49984b MV |
159 | |
160 | /* | |
161 | * GPIO settings | |
162 | */ | |
163 | #define CONFIG_SYS_GPSR0_VAL 0x00000000 | |
164 | #define CONFIG_SYS_GPSR1_VAL 0x00020000 | |
165 | #define CONFIG_SYS_GPSR2_VAL 0x0002C000 | |
166 | #define CONFIG_SYS_GPSR3_VAL 0x00000000 | |
167 | ||
168 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | |
169 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
170 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
171 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 | |
172 | ||
173 | #define CONFIG_SYS_GPDR0_VAL 0x08000000 | |
174 | #define CONFIG_SYS_GPDR1_VAL 0x0002A981 | |
175 | #define CONFIG_SYS_GPDR2_VAL 0x0202FC00 | |
176 | #define CONFIG_SYS_GPDR3_VAL 0x00000000 | |
177 | ||
178 | #define CONFIG_SYS_GAFR0_L_VAL 0x00100000 | |
179 | #define CONFIG_SYS_GAFR0_U_VAL 0x00C00010 | |
180 | #define CONFIG_SYS_GAFR1_L_VAL 0x999A901A | |
181 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008 | |
182 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA | |
183 | #define CONFIG_SYS_GAFR2_U_VAL 0x0109A000 | |
184 | #define CONFIG_SYS_GAFR3_L_VAL 0x54000300 | |
185 | #define CONFIG_SYS_GAFR3_U_VAL 0x00024001 | |
186 | ||
187 | #define CONFIG_SYS_PSSR_VAL 0x30 | |
188 | ||
189 | /* | |
190 | * Clock settings | |
191 | */ | |
192 | #define CONFIG_SYS_CKEN 0x00500240 | |
193 | #define CONFIG_SYS_CCCR 0x02000290 | |
194 | ||
195 | /* | |
196 | * Memory settings | |
197 | */ | |
198 | #define CONFIG_SYS_MSC0_VAL 0x000095f2 | |
199 | #define CONFIG_SYS_MSC1_VAL 0x00007ff4 | |
200 | #define CONFIG_SYS_MSC2_VAL 0x00000000 | |
201 | #define CONFIG_SYS_MDCNFG_VAL 0x08000ac9 | |
202 | #define CONFIG_SYS_MDREFR_VAL 0x2013e01e | |
203 | #define CONFIG_SYS_MDMRS_VAL 0x00320032 | |
204 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 | |
205 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 | |
206 | ||
207 | /* | |
208 | * PCMCIA and CF Interfaces | |
209 | */ | |
210 | #define CONFIG_SYS_MECR_VAL 0x00000001 | |
211 | #define CONFIG_SYS_MCMEM0_VAL 0x00014307 | |
212 | #define CONFIG_SYS_MCMEM1_VAL 0x00014307 | |
213 | #define CONFIG_SYS_MCATT0_VAL 0x0001c787 | |
214 | #define CONFIG_SYS_MCATT1_VAL 0x0001c787 | |
215 | #define CONFIG_SYS_MCIO0_VAL 0x0001430f | |
216 | #define CONFIG_SYS_MCIO1_VAL 0x0001430f | |
217 | ||
67a1f00c | 218 | #include "pxa-common.h" |
2e49984b MV |
219 | |
220 | #endif /* __CONFIG_H */ |