[thirdparty/u-boot.git] / include / configs / colibri_pxa270.h

/*
 * Toradex Colibri PXA270 configuration file
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define	CONFIG_SYS_TEXT_BASE		0x0
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT		0x40000

/* We will never enable dcache because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
#define	CONFIG_ARCH_CPU_INIT
#define	CONFIG_BOOTCOMMAND						\
	"if fatload mmc 0 0xa0000000 uImage; then "			\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"bootm 0xc0000;"
#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_LZMA			/* LZMA compression support */

/*
 * Serial Console Configuration
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_FFUART			1
#define CONFIG_CONS_INDEX		3
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#define	CONFIG_CMD_ENV
#define	CONFIG_CMD_MMC

/* I2C support */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PXA
#define CONFIG_PXA_STD_I2C
#define CONFIG_PXA_PWR_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#endif

/* LCD support */
#ifdef CONFIG_LCD
#define CONFIG_PXA_LCD
#define CONFIG_PXA_VGA
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES	10
#define CONFIG_CMD_BMP
#define CONFIG_LCD_LOGO
#endif

/*
 * Networking Configuration
 */
#ifdef	CONFIG_CMD_NET

#define	CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_BASE		0x08000000
#define DM9000_IO			(CONFIG_DM9000_BASE)
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define	CONFIG_NET_RETRY_COUNT		10

#define	CONFIG_BOOTP_BOOTFILESIZE
#define	CONFIG_BOOTP_BOOTPATH
#define	CONFIG_BOOTP_GATEWAY
#define	CONFIG_BOOTP_HOSTNAME
#endif

#undef	CONFIG_SYS_LONGHELP		/* Saves 10 KB */
#define	CONFIG_SYS_CBSIZE		256
#define	CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		16
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define	CONFIG_SYS_DEVICE_NULLDEV	1
#define	CONFIG_CMDLINE_EDITING		1
#define	CONFIG_AUTO_COMPLETE		1

/*
 * Clock Configuration
 */
#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

/*
 * NOR FLASH
 */
#ifdef	CONFIG_CMD_FLASH
#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define	CONFIG_SYS_FLASH_CFI
#define	CONFIG_FLASH_CFI_DRIVER		1
#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT

#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
#define	CONFIG_SYS_MAX_FLASH_BANKS	1

#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_LOCK_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(25 * CONFIG_SYS_HZ)

#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define	CONFIG_SYS_FLASH_PROTECTION		1

#define CONFIG_ENV_IS_IN_FLASH		1

#else	/* No flash */
#define	CONFIG_SYS_NO_FLASH
#define	CONFIG_ENV_IS_NOWHERE
#endif

#define	CONFIG_SYS_MONITOR_BASE		0x0
#define	CONFIG_SYS_MONITOR_LEN		0x40000

/* Skip factory configuration block */
#define	CONFIG_ENV_ADDR			\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
#define	CONFIG_ENV_SIZE			0x40000
#define	CONFIG_ENV_SECT_SIZE		0x40000

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GPSR0_VAL	0x00000000
#define	CONFIG_SYS_GPSR1_VAL	0x00020000
#define	CONFIG_SYS_GPSR2_VAL	0x0002c000
#define	CONFIG_SYS_GPSR3_VAL	0x00000000

#define	CONFIG_SYS_GPCR0_VAL	0x00000000
#define	CONFIG_SYS_GPCR1_VAL	0x00000000
#define	CONFIG_SYS_GPCR2_VAL	0x00000000
#define	CONFIG_SYS_GPCR3_VAL	0x00000000

#define	CONFIG_SYS_GPDR0_VAL	0xc8008000
#define	CONFIG_SYS_GPDR1_VAL	0xfc02a981
#define	CONFIG_SYS_GPDR2_VAL	0x92c3ffff
#define	CONFIG_SYS_GPDR3_VAL	0x0061e804

#define	CONFIG_SYS_GAFR0_L_VAL	0x80100000
#define	CONFIG_SYS_GAFR0_U_VAL	0xa5c00010
#define	CONFIG_SYS_GAFR1_L_VAL	0x6992901a
#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa50008
#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
#define	CONFIG_SYS_GAFR2_U_VAL	0x4109a002
#define	CONFIG_SYS_GAFR3_L_VAL	0x54000310
#define	CONFIG_SYS_GAFR3_U_VAL	0x00005401

#define	CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0x00500240
#define	CONFIG_SYS_CCCR		0x02000290

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x9ee1c5f2
#define	CONFIG_SYS_MSC1_VAL	0x9ee1f994
#define	CONFIG_SYS_MSC2_VAL	0x9ee19ee1
#define	CONFIG_SYS_MDCNFG_VAL	0x090009c9
#define	CONFIG_SYS_MDREFR_VAL	0x2003a031
#define	CONFIG_SYS_MDMRS_VAL	0x00220022
#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
#define	CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000000
#define	CONFIG_SYS_MCMEM0_VAL	0x00028307
#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
#define	CONFIG_SYS_MCATT0_VAL	0x00038787
#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
#define	CONFIG_SYS_MCIO0_VAL	0x0002830f
#define	CONFIG_SYS_MCIO1_VAL	0x0001430f

#include "pxa-common.h"

#endif /* __CONFIG_H */
Commit	Line	Data
2e49984b MV	1	/*
	2	* Toradex Colibri PXA270 configuration file
	3	*
	4	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
85559679	5	* Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
2e49984b	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
2e49984b MV	8	*/
2e49984b MV	9
7c49b523 MZ	10	#ifndef __CONFIG_H
7c49b523 MZ	11	#define __CONFIG_H
2e49984b MV	12
	13	/*
	14	* High Level Board Configuration Options
	15	*/
abc20aba	16	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
f9f5486c	17	#define CONFIG_SYS_TEXT_BASE 0x0
7c49b523 MZ	18	/* Avoid overwriting factory configuration block */
7c49b523 MZ	19	#define CONFIG_BOARD_SIZE_LIMIT 0x40000
2e49984b	20
4f9bbd9e MZ	21	/* We will never enable dcache because we have to setup MMU first */
	22	#define CONFIG_SYS_DCACHE_OFF
	23
2e49984b MV	24	/*
	25	* Environment settings
	26	*/
f9f5486c MV	27	#define CONFIG_ENV_OVERWRITE
	28	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	29	#define CONFIG_ARCH_CPU_INIT
2e49984b	30	#define CONFIG_BOOTCOMMAND \
99d672fa	31	"if fatload mmc 0 0xa0000000 uImage; then " \
2e49984b MV	32	"bootm 0xa0000000; " \
	33	"fi; " \
	34	"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
	35	"bootm 0xa0000000; " \
	36	"fi; " \
99d672fa	37	"bootm 0xc0000;"
2e49984b MV	38	#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
	39	#define CONFIG_TIMESTAMP
	40	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	41	#define CONFIG_CMDLINE_TAG
	42	#define CONFIG_SETUP_MEMORY_TAGS
2e49984b MV	43	#define CONFIG_LZMA /* LZMA compression support */
	44
	45	/*
	46	* Serial Console Configuration
	47	*/
	48	#define CONFIG_PXA_SERIAL
	49	#define CONFIG_FFUART 1
ce6971cd	50	#define CONFIG_CONS_INDEX 3
2e49984b	51	#define CONFIG_BAUDRATE 115200
2e49984b MV	52
	53	/*
	54	* Bootloader Components Configuration
	55	*/
2e49984b	56	#define CONFIG_CMD_ENV
2e49984b	57	#define CONFIG_CMD_MMC
2e49984b	58
3664fa1b MZ	59	/* I2C support */
3664fa1b MZ	60	#ifdef CONFIG_SYS_I2C
3664fa1b MZ	61	#define CONFIG_SYS_I2C_PXA
	62	#define CONFIG_PXA_STD_I2C
	63	#define CONFIG_PXA_PWR_I2C
	64	#define CONFIG_SYS_I2C_SPEED 100000
	65	#endif
	66
4f9bbd9e MZ	67	/* LCD support */
	68	#ifdef CONFIG_LCD
	69	#define CONFIG_PXA_LCD
	70	#define CONFIG_PXA_VGA
	71	#define CONFIG_SYS_WHITE_ON_BLACK
	72	#define CONFIG_CONSOLE_SCROLL_LINES 10
	73	#define CONFIG_CMD_BMP
	74	#define CONFIG_LCD_LOGO
	75	#endif
	76
2e49984b MV	77	/*
2e49984b MV	78	* Networking Configuration
2e49984b MV	79	*/
2e49984b MV	80	#ifdef CONFIG_CMD_NET
2e49984b	81
2e49984b MV	82	#define CONFIG_DRIVER_DM9000 1
	83	#define CONFIG_DM9000_BASE 0x08000000
	84	#define DM9000_IO (CONFIG_DM9000_BASE)
	85	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	86	#define CONFIG_NET_RETRY_COUNT 10
	87
	88	#define CONFIG_BOOTP_BOOTFILESIZE
	89	#define CONFIG_BOOTP_BOOTPATH
	90	#define CONFIG_BOOTP_GATEWAY
	91	#define CONFIG_BOOTP_HOSTNAME
	92	#endif
	93
fe488a85	94	#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
f9f5486c MV	95	#define CONFIG_SYS_CBSIZE 256
	96	#define CONFIG_SYS_PBSIZE \
	97	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	98	#define CONFIG_SYS_MAXARGS 16
	99	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
2e49984b	100	#define CONFIG_SYS_DEVICE_NULLDEV 1
f9f5486c MV	101	#define CONFIG_CMDLINE_EDITING 1
	102	#define CONFIG_AUTO_COMPLETE 1
	103
2e49984b MV	104	/*
	105	* Clock Configuration
	106	*/
f9f5486c	107	#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
2e49984b	108
2e49984b MV	109	/*
	110	* DRAM Map
	111	*/
	112	#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
	113	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	114	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	115
	116	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	117	#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
	118
	119	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	120	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	121
f9f5486c	122	#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
6ef6eb91	123	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
f9f5486c	124	#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
6ef6eb91	125
2e49984b MV	126	/*
	127	* NOR FLASH
	128	*/
	129	#ifdef CONFIG_CMD_FLASH
	130	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
d817889b	131	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
2e49984b MV	132	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	133
	134	#define CONFIG_SYS_FLASH_CFI
	135	#define CONFIG_FLASH_CFI_DRIVER 1
d817889b	136	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
2e49984b MV	137
	138	#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
	139	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	140
f9f5486c MV	141	#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
f9f5486c MV	142	#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
d817889b MZ	143	#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
d817889b MZ	144	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
2e49984b MV	145
	146	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	147	#define CONFIG_SYS_FLASH_PROTECTION 1
	148
	149	#define CONFIG_ENV_IS_IN_FLASH 1
	150
	151	#else /* No flash */
	152	#define CONFIG_SYS_NO_FLASH
50dea462	153	#define CONFIG_ENV_IS_NOWHERE
2e49984b MV	154	#endif
2e49984b MV	155
f9f5486c	156	#define CONFIG_SYS_MONITOR_BASE 0x0
7c49b523	157	#define CONFIG_SYS_MONITOR_LEN 0x40000
2e49984b	158
7c49b523	159	/* Skip factory configuration block */
f9f5486c	160	#define CONFIG_ENV_ADDR \
7c49b523	161	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
f9f5486c MV	162	#define CONFIG_ENV_SIZE 0x40000
f9f5486c MV	163	#define CONFIG_ENV_SECT_SIZE 0x40000
2e49984b MV	164
	165	/*
	166	* GPIO settings
	167	*/
	168	#define CONFIG_SYS_GPSR0_VAL 0x00000000
	169	#define CONFIG_SYS_GPSR1_VAL 0x00020000
44ba7a37	170	#define CONFIG_SYS_GPSR2_VAL 0x0002c000
2e49984b MV	171	#define CONFIG_SYS_GPSR3_VAL 0x00000000
	172
	173	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	174	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	175	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	176	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	177
44ba7a37 MZ	178	#define CONFIG_SYS_GPDR0_VAL 0xc8008000
	179	#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
	180	#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
	181	#define CONFIG_SYS_GPDR3_VAL 0x0061e804
2e49984b	182
44ba7a37 MZ	183	#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
	184	#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
	185	#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
	186	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
	187	#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
	188	#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
	189	#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
	190	#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
2e49984b MV	191
	192	#define CONFIG_SYS_PSSR_VAL 0x30
	193
	194	/*
	195	* Clock settings
	196	*/
	197	#define CONFIG_SYS_CKEN 0x00500240
	198	#define CONFIG_SYS_CCCR 0x02000290
	199
	200	/*
	201	* Memory settings
	202	*/
44ba7a37 MZ	203	#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
	204	#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
	205	#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
	206	#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
	207	#define CONFIG_SYS_MDREFR_VAL 0x2003a031
	208	#define CONFIG_SYS_MDMRS_VAL 0x00220022
	209	#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
2e49984b MV	210	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	211
	212	/*
	213	* PCMCIA and CF Interfaces
	214	*/
44ba7a37 MZ	215	#define CONFIG_SYS_MECR_VAL 0x00000000
44ba7a37 MZ	216	#define CONFIG_SYS_MCMEM0_VAL 0x00028307
2e49984b	217	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
44ba7a37	218	#define CONFIG_SYS_MCATT0_VAL 0x00038787
2e49984b	219	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
44ba7a37	220	#define CONFIG_SYS_MCIO0_VAL 0x0002830f
2e49984b MV	221	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
2e49984b MV	222
67a1f00c	223	#include "pxa-common.h"
2e49984b	224
7c49b523	225	#endif /* __CONFIG_H */