[thirdparty/u-boot.git] / include / configs / corenet_ds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2009-2012 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * Corenet DS style board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

#include "../board/freescale/common/ics307_clk.h"

#ifdef CONFIG_RAMBOOT_PBL
#ifdef CONFIG_NXP_ESBC
#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_RAMBOOT_NAND
#endif
#define CONFIG_BOOTSCRIPT_COPY_RAM
#else
#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
#endif
#endif

#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

/* High Level Configuration Options */
#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1			/* PCIE controller 1 */
#define CONFIG_PCIE2			/* PCIE controller 2 */

#if defined(CONFIG_SPIFLASH)
#elif defined(CONFIG_SDCARD)
#define CONFIG_FSL_FIXED_MMC_LOCATION
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_SYS_CACHE_STASHING
#define CONFIG_BACKSIDE_L2_CACHE
#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

#define CONFIG_ENABLE_36BIT_PHYS

#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
#endif
#define CONFIG_SYS_L3_SIZE		(1024 << 10)
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
#endif

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

#define CONFIG_SYS_SPD_BUS_NUM	1
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * Local Bus Definitions
 */

/* Set the local bus clock 1/8 of platform clock */
#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8

#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_FLASH_BR_PRELIM \
		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
		 | BR_PS_16 | BR_V)
#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)

#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS		0xfffdf0000ull
#else
#define PIXIS_BASE_PHYS		PIXIS_BASE
#endif

#define PIXIS_LBMAP_SWITCH	7
#define PIXIS_LBMAP_MASK	0xf0
#define PIXIS_LBMAP_SHIFT	4
#define PIXIS_LBMAP_ALTBANK	0x40

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif

/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BASE		0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
#endif

#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
			       | BR_PS_8	       /* Port Size = 8 bit */ \
			       | BR_MS_FCM	       /* MSEL = FCM */ \
			       | BR_V)		       /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
			       | OR_FCM_PGS	       /* Large Page*/ \
			       | OR_FCM_CSCT \
			       | OR_FCM_CST \
			       | OR_FCM_CHT \
			       | OR_FCM_SCY_1 \
			       | OR_FCM_TRLX \
			       | OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */

/*
 * RapidIO
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */

#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
#else
#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */

/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */

/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */

/*
 * SRIO_PCIE_BOOT - SLAVE
 */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull

/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS	10
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	10
#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

/* SATA */
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

#define CONFIG_LBA48
#endif

#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4

#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0

#define CONFIG_SYS_TBIPA_VALUE	8
#endif

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_HAS_FSL_MPH_USB

#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif

#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */

#ifdef CONFIG_TARGET_P4080DS
#define __USB_PHY_TYPE	ulpi
#else
#define __USB_PHY_TYPE	utmi
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
	"bank_intlv=cs0_cs1;"					\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=p4080ds/p4080ds.dtb\0"				\
	"bdev=sda3\0"

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
d1712369	2	/*
3d7506fa	3	* Copyright 2009-2012 Freescale Semiconductor, Inc.
a97a071d	4	* Copyright 2020-2021 NXP
d1712369 KG	5	*/
	6
	7	/*
	8	* Corenet DS style board configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
1af3c7f4 SG	13	#include <linux/stringify.h>
1af3c7f4 SG	14
d1712369 KG	15	#include "../board/freescale/common/ics307_clk.h"
d1712369 KG	16
2a9fab82	17	#ifdef CONFIG_RAMBOOT_PBL
bef18454	18	#ifdef CONFIG_NXP_ESBC
467a40df AB	19	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
467a40df AB	20	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
88718be3	21	#ifdef CONFIG_MTD_RAW_NAND
467a40df AB	22	#define CONFIG_RAMBOOT_NAND
467a40df AB	23	#endif
5050f6f0	24	#define CONFIG_BOOTSCRIPT_COPY_RAM
467a40df	25	#else
2a9fab82 SX	26	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
	27	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
	28	#endif
467a40df	29	#endif
2a9fab82	30
461632bd	31	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
292dc6c5	32	/* Set 1M boot space */
461632bd LG	33	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
	34	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	35	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
292dc6c5	36	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
292dc6c5 LG	37	#endif
292dc6c5 LG	38
d1712369	39	/* High Level Configuration Options */
d1712369	40	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
d1712369	41
7a577fda KG	42	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	43	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	44	#endif
	45
d1712369	46	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
51370d56	47	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
b38eaec5 RD	48	#define CONFIG_PCIE1 /* PCIE controller 1 */
b38eaec5 RD	49	#define CONFIG_PCIE2 /* PCIE controller 2 */
d1712369	50
be827c7a	51	#if defined(CONFIG_SPIFLASH)
be827c7a	52	#elif defined(CONFIG_SDCARD)
4394d0c2	53	#define CONFIG_FSL_FIXED_MMC_LOCATION
d1712369 KG	54	#endif
d1712369 KG	55
d1712369 KG	56	/*
	57	* These can be toggled for performance analysis, otherwise use default.
	58	*/
	59	#define CONFIG_SYS_CACHE_STASHING
	60	#define CONFIG_BACKSIDE_L2_CACHE
	61	#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
d1712369	62	#ifdef CONFIG_DDR_ECC
d1712369 KG	63	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	64	#endif
	65
	66	#define CONFIG_ENABLE_36BIT_PHYS
d1712369	67
4672e1ea	68	#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
d1712369	69
2a9fab82 SX	70	/*
	71	* Config the L3 Cache as L3 SRAM
	72	*/
	73	#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
	74	#ifdef CONFIG_PHYS_64BIT
	75	#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull \| CONFIG_RAMBOOT_TEXT_BASE)
	76	#else
	77	#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
	78	#endif
	79	#define CONFIG_SYS_L3_SIZE (1024 << 10)
	80	#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
	81
d1712369 KG	82	#ifdef CONFIG_PHYS_64BIT
	83	#define CONFIG_SYS_DCSRBAR 0xf0000000
	84	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	85	#endif
	86
	87	/* EEPROM */
d1712369 KG	88	#define CONFIG_SYS_I2C_EEPROM_NXID
d1712369 KG	89	#define CONFIG_SYS_EEPROM_BUS_NUM 0
d1712369 KG	90
	91	/*
	92	* DDR Setup
	93	*/
	94	#define CONFIG_VERY_BIG_RAM
	95	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	96	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	97
	98	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
d1712369	99
d1712369 KG	100	#define CONFIG_SYS_SPD_BUS_NUM 1
	101	#define SPD_EEPROM_ADDRESS1 0x51
	102	#define SPD_EEPROM_ADDRESS2 0x52
e02aea61	103	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
28a96671	104	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
d1712369 KG	105
	106	/*
	107	* Local Bus Definitions
	108	*/
	109
	110	/* Set the local bus clock 1/8 of platform clock */
	111	#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
	112
	113	#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
	114	#ifdef CONFIG_PHYS_64BIT
	115	#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
	116	#else
	117	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	118	#endif
	119
374a235d	120	#define CONFIG_SYS_FLASH_BR_PRELIM \
7ee41107	121	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
374a235d SX	122	\| BR_PS_16 \| BR_V)
374a235d SX	123	#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
d1712369 KG	124	\| OR_GPCM_SCY_8 \| OR_GPCM_EHTR_CLEAR)
d1712369 KG	125
d1712369 KG	126	#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
	127	#ifdef CONFIG_PHYS_64BIT
	128	#define PIXIS_BASE_PHYS 0xfffdf0000ull
	129	#else
	130	#define PIXIS_BASE_PHYS PIXIS_BASE
	131	#endif
	132
d1712369 KG	133	#define PIXIS_LBMAP_SWITCH 7
	134	#define PIXIS_LBMAP_MASK 0xf0
	135	#define PIXIS_LBMAP_SHIFT 4
	136	#define PIXIS_LBMAP_ALTBANK 0x40
	137
	138	#define CONFIG_SYS_FLASH_QUIET_TEST
0cf207ec	139	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
d1712369	140
d1712369 KG	141	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	142	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	143	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	144
14d0a02a	145	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
d1712369	146
2a9fab82 SX	147	#if defined(CONFIG_RAMBOOT_PBL)
	148	#define CONFIG_SYS_RAMBOOT
	149	#endif
	150
e02aea61	151	/* Nand Flash */
e02aea61 KG	152	#ifdef CONFIG_NAND_FSL_ELBC
	153	#define CONFIG_SYS_NAND_BASE 0xffa00000
	154	#ifdef CONFIG_PHYS_64BIT
	155	#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
	156	#else
	157	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	158	#endif
	159
	160	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
	161	#define CONFIG_SYS_MAX_NAND_DEVICE 1
e02aea61 KG	162
	163	/* NAND flash config */
	164	#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	165	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	166	\| BR_PS_8 /* Port Size = 8 bit */ \
	167	\| BR_MS_FCM /* MSEL = FCM */ \
	168	\| BR_V) /* valid */
	169	#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
	170	\| OR_FCM_PGS /* Large Page*/ \
	171	\| OR_FCM_CSCT \
	172	\| OR_FCM_CST \
	173	\| OR_FCM_CHT \
	174	\| OR_FCM_SCY_1 \
	175	\| OR_FCM_TRLX \
	176	\| OR_FCM_EHTR)
c6d33901	177	#endif /* CONFIG_NAND_FSL_ELBC */
e02aea61	178
d1712369	179	#define CONFIG_SYS_FLASH_EMPTY_INFO
d1712369 KG	180	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
d1712369 KG	181
d1712369 KG	182	#define CONFIG_HWCONFIG
	183
	184	/* define to use L1 as initial stack */
	185	#define CONFIG_L1_INIT_RAM
	186	#define CONFIG_SYS_INIT_RAM_LOCK
	187	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	188	#ifdef CONFIG_PHYS_64BIT
	189	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
	190	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
	191	/* The assembler doesn't like typecast */
	192	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	193	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	194	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	195	#else
	196	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
	197	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
	198	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
	199	#endif
553f0982	200	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
d1712369	201
25ddd1fb	202	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
d1712369 KG	203	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d1712369 KG	204
9307cbab	205	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
d1712369 KG	206
	207	/* Serial Port - controlled on board with jumper J8
	208	* open - index 2
	209	* shorted - index 1
	210	*/
d1712369 KG	211	#define CONFIG_SYS_NS16550_SERIAL
	212	#define CONFIG_SYS_NS16550_REG_SIZE 1
	213	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	214
	215	#define CONFIG_SYS_BAUDRATE_TABLE \
	216	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	217
	218	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	219	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	220	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	221	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	222
d1712369	223	/* I2C */
d1712369 KG	224
	225	/*
	226	* RapidIO
	227	*/
a09b9b68	228	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
d1712369	229	#ifdef CONFIG_PHYS_64BIT
a09b9b68	230	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
d1712369	231	#else
a09b9b68	232	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
d1712369	233	#endif
a09b9b68	234	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
d1712369	235
a09b9b68	236	#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
d1712369	237	#ifdef CONFIG_PHYS_64BIT
a09b9b68	238	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
d1712369	239	#else
a09b9b68	240	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
d1712369	241	#endif
a09b9b68	242	#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
d1712369	243
5ffa88ec LG	244	/*
	245	* for slave u-boot IMAGE instored in master memory space,
	246	* PHYS must be aligned based on the SIZE
	247	*/
e4911815 LG	248	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	249	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	250	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	251	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
3f1af81b	252	/*
ff65f126	253	* for slave UCODE and ENV instored in master memory space,
3f1af81b LG	254	* PHYS must be aligned based on the SIZE
3f1af81b LG	255	*/
e4911815	256	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
b5f7c873 LG	257	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
b5f7c873 LG	258	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
ff65f126	259
5056c8e0	260	/* slave core release by master*/
b5f7c873 LG	261	#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
b5f7c873 LG	262	#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
5ffa88ec	263
292dc6c5	264	/*
461632bd	265	* SRIO_PCIE_BOOT - SLAVE
292dc6c5	266	*/
461632bd LG	267	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	268	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	269	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	270	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
292dc6c5 LG	271	#endif
292dc6c5 LG	272
2dd3095d SX	273	/*
	274	* eSPI - Enhanced SPI
	275	*/
2dd3095d	276
d1712369 KG	277	/*
	278	* General PCI
	279	* Memory space is mapped 1-1, but I/O space must start from 0.
	280	*/
	281
	282	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	283	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
d1712369	284	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
d1712369	285	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
d1712369	286	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
d1712369 KG	287
	288	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	289	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
d1712369	290	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
d1712369	291	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
d1712369	292	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
d1712369 KG	293
d1712369 KG	294	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
02bb4989	295	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
d1712369	296	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
d1712369	297	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
d1712369	298	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
d1712369	299
1bf8e9fd	300	/* controller 4, Base address 203000 */
1bf8e9fd	301	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
1bf8e9fd	302	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
1bf8e9fd	303
d1712369 KG	304	/* Qman/Bman */
	305	#define CONFIG_SYS_BMAN_NUM_PORTALS 10
	306	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	307	#ifdef CONFIG_PHYS_64BIT
	308	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	309	#else
	310	#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
	311	#endif
	312	#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
3fa66db4 JL	313	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	314	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	315	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	316	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	317	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	318	CONFIG_SYS_BMAN_CENA_SIZE)
	319	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	320	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
d1712369 KG	321	#define CONFIG_SYS_QMAN_NUM_PORTALS 10
	322	#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
	323	#ifdef CONFIG_PHYS_64BIT
	324	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
	325	#else
	326	#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
	327	#endif
	328	#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
3fa66db4 JL	329	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	330	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	331	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	332	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	333	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	334	CONFIG_SYS_QMAN_CENA_SIZE)
	335	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	336	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
d1712369 KG	337
	338	#define CONFIG_SYS_DPAA_FMAN
	339	#define CONFIG_SYS_DPAA_PME
f2717b47	340	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
d1712369	341
d1712369	342	#ifdef CONFIG_PCI
d1712369	343	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
d1712369 KG	344	#endif /* CONFIG_PCI */
	345
	346	/* SATA */
	347	#ifdef CONFIG_FSL_SATA_V2
d1712369 KG	348	#define CONFIG_SATA1
	349	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	350	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	351	#define CONFIG_SATA2
	352	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	353	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	354
	355	#define CONFIG_LBA48
d1712369 KG	356	#endif
	357
	358	#ifdef CONFIG_FMAN_ENET
	359	#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
	360	#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
	361	#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
	362	#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
	363	#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
	364
d1712369 KG	365	#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
	366	#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
	367	#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
	368	#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
	369	#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
d1712369 KG	370
d1712369 KG	371	#define CONFIG_SYS_TBIPA_VALUE 8
d1712369 KG	372	#endif
	373
	374	/*
	375	* Environment
	376	*/
d1712369 KG	377	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	378	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	379
d1712369 KG	380	/*
	381	* USB
	382	*/
3d7506fa	383	#define CONFIG_HAS_FSL_DR_USB
	384	#define CONFIG_HAS_FSL_MPH_USB
	385
	386	#if defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB)
d1712369	387	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
3d7506fa	388	#endif
d1712369	389
d1712369	390	#ifdef CONFIG_MMC
d1712369 KG	391	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
d1712369 KG	392	#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
d1712369 KG	393	#endif
	394
	395	/*
	396	* Miscellaneous configurable options
	397	*/
d1712369 KG	398
	399	/*
	400	* For booting Linux, the board info and command line data
a832ac41	401	* have to be in the first 64 MB of memory, since this is
d1712369 KG	402	* the maximum mapped by the Linux kernel during initialization.
d1712369 KG	403	*/
a832ac41 KG	404	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	405	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
d1712369	406
d1712369 KG	407	/*
	408	* Environment Configuration
	409	*/
8b3637c6	410	#define CONFIG_ROOTPATH "/opt/nfsroot"
d1712369 KG	411	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
d1712369 KG	412
529fb062	413	#ifdef CONFIG_TARGET_P4080DS
68d4230c RM	414	#define __USB_PHY_TYPE ulpi
	415	#else
	416	#define __USB_PHY_TYPE utmi
	417	#endif
	418
d1712369	419	#define CONFIG_EXTRA_ENV_SETTINGS \
c2b3b640	420	"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
68d4230c	421	"bank_intlv=cs0_cs1;" \
55964bb6	422	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
55964bb6	423	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
d1712369	424	"netdev=eth0\0" \
5368c55d MV	425	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
5368c55d MV	426	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
c2b3b640 EM	427	"tftpflash=tftpboot $loadaddr $uboot && " \
	428	"protect off $ubootaddr +$filesize && " \
	429	"erase $ubootaddr +$filesize && " \
	430	"cp.b $loadaddr $ubootaddr $filesize && " \
	431	"protect on $ubootaddr +$filesize && " \
	432	"cmp.b $loadaddr $ubootaddr $filesize\0" \
d1712369 KG	433	"consoledev=ttyS0\0" \
	434	"ramdiskaddr=2000000\0" \
	435	"ramdiskfile=p4080ds/ramdisk.uboot\0" \
b24a4f62	436	"fdtaddr=1e00000\0" \
d1712369	437	"fdtfile=p4080ds/p4080ds.dtb\0" \
3246584d	438	"bdev=sda3\0"
d1712369	439
7065b7d4	440	#include <asm/fsl_secure_boot.h>
7065b7d4	441
d1712369	442	#endif /* __CONFIG_H */