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1 | /* |
2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Corenet DS style board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #include "../board/freescale/common/ics307_clk.h" | |
30 | ||
31 | /* High Level Configuration Options */ | |
32 | #define CONFIG_BOOKE | |
33 | #define CONFIG_E500 /* BOOKE e500 family */ | |
34 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
35 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
36 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
37 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
38 | #define CONFIG_MP /* support multiple processors */ | |
39 | ||
40 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
41 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
42 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
43 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
44 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
45 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
46 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
47 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
48 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
49 | #define CONFIG_SYS_HAS_SERDES /* has SERDES */ | |
50 | ||
51 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
52 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
53 | ||
54 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
55 | ||
56 | #define CONFIG_ENV_OVERWRITE | |
57 | ||
58 | #ifdef CONFIG_SYS_NO_FLASH | |
59 | #define CONFIG_ENV_IS_NOWHERE | |
60 | #else | |
61 | #define CONFIG_ENV_IS_IN_FLASH | |
62 | #define CONFIG_FLASH_CFI_DRIVER | |
63 | #define CONFIG_SYS_FLASH_CFI | |
64 | #endif | |
65 | ||
66 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
67 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ | |
68 | ||
69 | /* | |
70 | * These can be toggled for performance analysis, otherwise use default. | |
71 | */ | |
72 | #define CONFIG_SYS_CACHE_STASHING | |
73 | #define CONFIG_BACKSIDE_L2_CACHE | |
74 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
75 | #define CONFIG_BTB /* toggle branch predition */ | |
2d941de9 | 76 | /*#define CONFIG_DDR_ECC*/ |
d1712369 KG |
77 | #ifdef CONFIG_DDR_ECC |
78 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
79 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
80 | #endif | |
81 | ||
82 | #define CONFIG_ENABLE_36BIT_PHYS | |
83 | ||
84 | #ifdef CONFIG_PHYS_64BIT | |
85 | #define CONFIG_ADDR_MAP | |
86 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
87 | #endif | |
88 | ||
4672e1ea | 89 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
90 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
91 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
92 | #define CONFIG_SYS_ALT_MEMTEST | |
93 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
94 | ||
95 | /* | |
96 | * Base addresses -- Note these are effective addresses where the | |
97 | * actual resources get mapped (not physical addresses) | |
98 | */ | |
99 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ | |
100 | #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ | |
101 | #ifdef CONFIG_PHYS_64BIT | |
102 | #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ | |
103 | #else | |
104 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
105 | #endif | |
106 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
107 | ||
108 | #ifdef CONFIG_PHYS_64BIT | |
109 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
110 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
111 | #endif | |
112 | ||
113 | /* EEPROM */ | |
114 | #define CONFIG_ID_EEPROM | |
115 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
116 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
117 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
118 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
119 | ||
120 | /* | |
121 | * DDR Setup | |
122 | */ | |
123 | #define CONFIG_VERY_BIG_RAM | |
124 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
126 | ||
127 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 128 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
129 | |
130 | #define CONFIG_DDR_SPD | |
131 | #define CONFIG_FSL_DDR3 | |
132 | ||
d1712369 KG |
133 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
134 | #define SPD_EEPROM_ADDRESS1 0x51 | |
135 | #define SPD_EEPROM_ADDRESS2 0x52 | |
28a96671 | 136 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
d1712369 KG |
137 | |
138 | /* | |
139 | * Local Bus Definitions | |
140 | */ | |
141 | ||
142 | /* Set the local bus clock 1/8 of platform clock */ | |
143 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
144 | ||
145 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
146 | #ifdef CONFIG_PHYS_64BIT | |
147 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
148 | #else | |
149 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
150 | #endif | |
151 | ||
152 | #define CONFIG_SYS_BR0_PRELIM \ | |
153 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ | |
154 | BR_PS_16 | BR_V) | |
155 | #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
156 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
157 | ||
158 | #define CONFIG_SYS_BR1_PRELIM \ | |
159 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
160 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
161 | ||
162 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ | |
163 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
164 | #ifdef CONFIG_PHYS_64BIT | |
165 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
166 | #else | |
167 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
168 | #endif | |
169 | ||
170 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
171 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
172 | ||
173 | #define PIXIS_LBMAP_SWITCH 7 | |
174 | #define PIXIS_LBMAP_MASK 0xf0 | |
175 | #define PIXIS_LBMAP_SHIFT 4 | |
176 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
177 | ||
178 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
179 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
180 | ||
181 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
182 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
183 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
184 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
185 | ||
14d0a02a | 186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 KG |
187 | |
188 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
189 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
190 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
191 | ||
192 | #define CONFIG_BOARD_EARLY_INIT_F | |
193 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
194 | #define CONFIG_MISC_INIT_R | |
195 | ||
196 | #define CONFIG_HWCONFIG | |
197 | ||
198 | /* define to use L1 as initial stack */ | |
199 | #define CONFIG_L1_INIT_RAM | |
200 | #define CONFIG_SYS_INIT_RAM_LOCK | |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
202 | #ifdef CONFIG_PHYS_64BIT | |
203 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
204 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
205 | /* The assembler doesn't like typecast */ | |
206 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
207 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
208 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
209 | #else | |
210 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
211 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
212 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
213 | #endif | |
214 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
215 | ||
216 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
217 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
218 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
219 | ||
220 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
221 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
222 | ||
223 | /* Serial Port - controlled on board with jumper J8 | |
224 | * open - index 2 | |
225 | * shorted - index 1 | |
226 | */ | |
227 | #define CONFIG_CONS_INDEX 1 | |
228 | #define CONFIG_SYS_NS16550 | |
229 | #define CONFIG_SYS_NS16550_SERIAL | |
230 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
231 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
232 | ||
233 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
234 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
235 | ||
236 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
237 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
238 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
239 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
240 | ||
241 | /* Use the HUSH parser */ | |
242 | #define CONFIG_SYS_HUSH_PARSER | |
243 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
244 | ||
245 | /* pass open firmware flat tree */ | |
246 | #define CONFIG_OF_LIBFDT | |
247 | #define CONFIG_OF_BOARD_SETUP | |
248 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
249 | ||
250 | /* new uImage format support */ | |
251 | #define CONFIG_FIT | |
252 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
253 | ||
254 | /* I2C */ | |
255 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
256 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
257 | #define CONFIG_I2C_MULTI_BUS | |
258 | #define CONFIG_I2C_CMD_TREE | |
259 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
260 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
261 | #define CONFIG_SYS_I2C_OFFSET 0x118000 | |
262 | #define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
263 | ||
264 | /* | |
265 | * RapidIO | |
266 | */ | |
267 | #define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 | |
268 | #ifdef CONFIG_PHYS_64BIT | |
269 | #define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull | |
270 | #else | |
271 | #define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 | |
272 | #endif | |
273 | #define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ | |
274 | ||
275 | #define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 | |
276 | #ifdef CONFIG_PHYS_64BIT | |
277 | #define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull | |
278 | #else | |
279 | #define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 | |
280 | #endif | |
281 | #define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ | |
282 | ||
283 | /* | |
284 | * General PCI | |
285 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
286 | */ | |
287 | ||
288 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
289 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
290 | #ifdef CONFIG_PHYS_64BIT | |
291 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
292 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
293 | #else | |
294 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
295 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
296 | #endif | |
297 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
298 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
299 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
300 | #ifdef CONFIG_PHYS_64BIT | |
301 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
302 | #else | |
303 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
304 | #endif | |
305 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
306 | ||
307 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
308 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
309 | #ifdef CONFIG_PHYS_64BIT | |
310 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
311 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
312 | #else | |
313 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
314 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
315 | #endif | |
316 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
317 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
318 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
319 | #ifdef CONFIG_PHYS_64BIT | |
320 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
321 | #else | |
322 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
323 | #endif | |
324 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
325 | ||
326 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
327 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 | |
328 | #ifdef CONFIG_PHYS_64BIT | |
329 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
330 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
331 | #else | |
332 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
333 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
334 | #endif | |
335 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
336 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
337 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
338 | #ifdef CONFIG_PHYS_64BIT | |
339 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
340 | #else | |
341 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
342 | #endif | |
343 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
344 | ||
1bf8e9fd KG |
345 | /* controller 4, Base address 203000 */ |
346 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
347 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
348 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
349 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
350 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
351 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
352 | ||
d1712369 KG |
353 | /* Qman/Bman */ |
354 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
355 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
356 | #ifdef CONFIG_PHYS_64BIT | |
357 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
358 | #else | |
359 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
360 | #endif | |
361 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
362 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
363 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
364 | #ifdef CONFIG_PHYS_64BIT | |
365 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
366 | #else | |
367 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
368 | #endif | |
369 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
370 | ||
371 | #define CONFIG_SYS_DPAA_FMAN | |
372 | #define CONFIG_SYS_DPAA_PME | |
373 | /* Default address of microcode for the Linux Fman driver */ | |
374 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 | |
375 | #ifdef CONFIG_PHYS_64BIT | |
376 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL | |
377 | #else | |
378 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR | |
379 | #endif | |
380 | ||
381 | #ifdef CONFIG_SYS_DPAA_FMAN | |
382 | #define CONFIG_FMAN_ENET | |
383 | #endif | |
384 | ||
385 | #ifdef CONFIG_PCI | |
386 | ||
387 | /*PCIE video card used*/ | |
388 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
389 | ||
390 | /* video */ | |
391 | #define CONFIG_VIDEO | |
392 | ||
393 | #ifdef CONFIG_VIDEO | |
394 | #define CONFIG_BIOSEMU | |
395 | #define CONFIG_CFB_CONSOLE | |
396 | #define CONFIG_VIDEO_SW_CURSOR | |
397 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
398 | #define CONFIG_ATI_RADEON_FB | |
399 | #define CONFIG_VIDEO_LOGO | |
400 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
401 | #endif | |
402 | ||
403 | #define CONFIG_NET_MULTI | |
404 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
405 | #define CONFIG_E1000 | |
406 | ||
407 | #ifndef CONFIG_PCI_PNP | |
408 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS | |
409 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
410 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
411 | #endif | |
412 | ||
413 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
414 | #define CONFIG_DOS_PARTITION | |
415 | #endif /* CONFIG_PCI */ | |
416 | ||
417 | /* SATA */ | |
418 | #ifdef CONFIG_FSL_SATA_V2 | |
419 | #define CONFIG_LIBATA | |
420 | #define CONFIG_FSL_SATA | |
421 | ||
422 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
423 | #define CONFIG_SATA1 | |
424 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
425 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
426 | #define CONFIG_SATA2 | |
427 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
428 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
429 | ||
430 | #define CONFIG_LBA48 | |
431 | #define CONFIG_CMD_SATA | |
432 | #define CONFIG_DOS_PARTITION | |
433 | #define CONFIG_CMD_EXT2 | |
434 | #endif | |
435 | ||
436 | #ifdef CONFIG_FMAN_ENET | |
437 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
438 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
439 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
440 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
441 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
442 | ||
443 | #if (CONFIG_SYS_NUM_FMAN == 2) | |
444 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c | |
445 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
446 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
447 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
448 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
449 | #endif | |
450 | ||
451 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
452 | #define CONFIG_MII /* MII PHY management */ | |
453 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
454 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
455 | #endif | |
456 | ||
457 | /* | |
458 | * Environment | |
459 | */ | |
460 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
461 | #define CONFIG_ENV_SIZE 0x2000 | |
462 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
463 | ||
464 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
465 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
466 | ||
467 | /* | |
468 | * Command line configuration. | |
469 | */ | |
470 | #include <config_cmd_default.h> | |
471 | ||
472 | #define CONFIG_CMD_ELF | |
473 | #define CONFIG_CMD_ERRATA | |
474 | #define CONFIG_CMD_IRQ | |
475 | #define CONFIG_CMD_I2C | |
476 | #define CONFIG_CMD_MII | |
477 | #define CONFIG_CMD_PING | |
478 | #define CONFIG_CMD_SETEXPR | |
479 | ||
480 | #ifdef CONFIG_PCI | |
481 | #define CONFIG_CMD_PCI | |
482 | #define CONFIG_CMD_NET | |
483 | #endif | |
484 | ||
485 | /* | |
486 | * USB | |
487 | */ | |
488 | #define CONFIG_CMD_USB | |
489 | #define CONFIG_USB_STORAGE | |
490 | #define CONFIG_USB_EHCI | |
491 | #define CONFIG_USB_EHCI_FSL | |
492 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
493 | #define CONFIG_CMD_EXT2 | |
494 | ||
495 | #define CONFIG_MMC | |
496 | ||
497 | #ifdef CONFIG_MMC | |
498 | #define CONFIG_FSL_ESDHC | |
499 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
500 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
501 | #define CONFIG_CMD_MMC | |
502 | #define CONFIG_GENERIC_MMC | |
503 | #define CONFIG_CMD_EXT2 | |
504 | #define CONFIG_CMD_FAT | |
505 | #define CONFIG_DOS_PARTITION | |
506 | #endif | |
507 | ||
508 | /* | |
509 | * Miscellaneous configurable options | |
510 | */ | |
511 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
512 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
513 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
514 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
515 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
516 | #ifdef CONFIG_CMD_KGDB | |
517 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
518 | #else | |
519 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
520 | #endif | |
521 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
522 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
523 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
524 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
525 | ||
526 | /* | |
527 | * For booting Linux, the board info and command line data | |
528 | * have to be in the first 16 MB of memory, since this is | |
529 | * the maximum mapped by the Linux kernel during initialization. | |
530 | */ | |
531 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
532 | ||
d1712369 KG |
533 | #ifdef CONFIG_CMD_KGDB |
534 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
535 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
536 | #endif | |
537 | ||
538 | /* | |
539 | * Environment Configuration | |
540 | */ | |
541 | #define CONFIG_ROOTPATH /opt/nfsroot | |
542 | #define CONFIG_BOOTFILE uImage | |
543 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
544 | ||
545 | /* default location for tftp and bootm */ | |
546 | #define CONFIG_LOADADDR 1000000 | |
547 | ||
548 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
549 | ||
550 | #define CONFIG_BAUDRATE 115200 | |
551 | ||
552 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
c2b3b640 EM |
553 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
554 | "bank_intlv=cs0_cs1\0" \ | |
d1712369 KG |
555 | "netdev=eth0\0" \ |
556 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
14d0a02a | 557 | "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ |
c2b3b640 EM |
558 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
559 | "protect off $ubootaddr +$filesize && " \ | |
560 | "erase $ubootaddr +$filesize && " \ | |
561 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
562 | "protect on $ubootaddr +$filesize && " \ | |
563 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
564 | "consoledev=ttyS0\0" \ |
565 | "ramdiskaddr=2000000\0" \ | |
566 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
567 | "fdtaddr=c00000\0" \ | |
568 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
569 | "bdev=sda3\0" \ | |
570 | "c=ffe\0" \ | |
571 | "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" | |
572 | ||
573 | #define CONFIG_HDBOOT \ | |
574 | "setenv bootargs root=/dev/$bdev rw " \ | |
575 | "console=$consoledev,$baudrate $othbootargs;" \ | |
576 | "tftp $loadaddr $bootfile;" \ | |
577 | "tftp $fdtaddr $fdtfile;" \ | |
578 | "bootm $loadaddr - $fdtaddr" | |
579 | ||
580 | #define CONFIG_NFSBOOTCOMMAND \ | |
581 | "setenv bootargs root=/dev/nfs rw " \ | |
582 | "nfsroot=$serverip:$rootpath " \ | |
583 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
584 | "console=$consoledev,$baudrate $othbootargs;" \ | |
585 | "tftp $loadaddr $bootfile;" \ | |
586 | "tftp $fdtaddr $fdtfile;" \ | |
587 | "bootm $loadaddr - $fdtaddr" | |
588 | ||
589 | #define CONFIG_RAMBOOTCOMMAND \ | |
590 | "setenv bootargs root=/dev/ram rw " \ | |
591 | "console=$consoledev,$baudrate $othbootargs;" \ | |
592 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
593 | "tftp $loadaddr $bootfile;" \ | |
594 | "tftp $fdtaddr $fdtfile;" \ | |
595 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
596 | ||
597 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
598 | ||
599 | #endif /* __CONFIG_H */ |