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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d1712369 | 2 | /* |
3d7506fa | 3 | * Copyright 2009-2012 Freescale Semiconductor, Inc. |
d1712369 KG |
4 | */ |
5 | ||
6 | /* | |
7 | * Corenet DS style board configuration file | |
8 | */ | |
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include "../board/freescale/common/ics307_clk.h" | |
13 | ||
2a9fab82 | 14 | #ifdef CONFIG_RAMBOOT_PBL |
467a40df AB |
15 | #ifdef CONFIG_SECURE_BOOT |
16 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
17 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
18 | #ifdef CONFIG_NAND | |
19 | #define CONFIG_RAMBOOT_NAND | |
20 | #endif | |
5050f6f0 | 21 | #define CONFIG_BOOTSCRIPT_COPY_RAM |
467a40df | 22 | #else |
2a9fab82 SX |
23 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
24 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e | 25 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg |
850af2c7 | 26 | #if defined(CONFIG_TARGET_P3041DS) |
e4536f8e | 27 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg |
529fb062 | 28 | #elif defined(CONFIG_TARGET_P4080DS) |
e4536f8e | 29 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg |
3b83649d | 30 | #elif defined(CONFIG_TARGET_P5020DS) |
e4536f8e | 31 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg |
161b4724 | 32 | #elif defined(CONFIG_TARGET_P5040DS) |
e4536f8e | 33 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg |
5d898a00 | 34 | #endif |
2a9fab82 | 35 | #endif |
467a40df | 36 | #endif |
2a9fab82 | 37 | |
461632bd | 38 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
292dc6c5 | 39 | /* Set 1M boot space */ |
461632bd LG |
40 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
41 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
42 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
292dc6c5 | 43 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
292dc6c5 LG |
44 | #endif |
45 | ||
d1712369 | 46 | /* High Level Configuration Options */ |
d1712369 | 47 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
d1712369 | 48 | |
7a577fda KG |
49 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
50 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
51 | #endif | |
52 | ||
d1712369 | 53 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
51370d56 | 54 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
b38eaec5 RD |
55 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
56 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
d1712369 | 57 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
d1712369 | 58 | |
d1712369 KG |
59 | #define CONFIG_ENV_OVERWRITE |
60 | ||
be827c7a | 61 | #if defined(CONFIG_SPIFLASH) |
be827c7a SX |
62 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
63 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
64 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
65 | #elif defined(CONFIG_SDCARD) | |
4394d0c2 | 66 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
be827c7a SX |
67 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
68 | #define CONFIG_ENV_SIZE 0x2000 | |
e222b1f3 | 69 | #define CONFIG_ENV_OFFSET (512 * 1658) |
374a235d | 70 | #elif defined(CONFIG_NAND) |
374a235d | 71 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
e222b1f3 | 72 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 73 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
0a85a9e7 LG |
74 | #define CONFIG_ENV_ADDR 0xffe20000 |
75 | #define CONFIG_ENV_SIZE 0x2000 | |
fd0451e4 LG |
76 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
77 | #define CONFIG_ENV_SIZE 0x2000 | |
be827c7a | 78 | #else |
2a9fab82 | 79 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
be827c7a SX |
80 | #define CONFIG_ENV_SIZE 0x2000 |
81 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
d1712369 KG |
82 | #endif |
83 | ||
84 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
d1712369 KG |
85 | |
86 | /* | |
87 | * These can be toggled for performance analysis, otherwise use default. | |
88 | */ | |
89 | #define CONFIG_SYS_CACHE_STASHING | |
90 | #define CONFIG_BACKSIDE_L2_CACHE | |
91 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
92 | #define CONFIG_BTB /* toggle branch predition */ | |
8ed20f2c | 93 | #define CONFIG_DDR_ECC |
d1712369 KG |
94 | #ifdef CONFIG_DDR_ECC |
95 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
96 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
97 | #endif | |
98 | ||
99 | #define CONFIG_ENABLE_36BIT_PHYS | |
100 | ||
101 | #ifdef CONFIG_PHYS_64BIT | |
102 | #define CONFIG_ADDR_MAP | |
103 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
104 | #endif | |
105 | ||
4672e1ea | 106 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
107 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
108 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d1712369 | 109 | |
2a9fab82 SX |
110 | /* |
111 | * Config the L3 Cache as L3 SRAM | |
112 | */ | |
113 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
114 | #ifdef CONFIG_PHYS_64BIT | |
115 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
116 | #else | |
117 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
118 | #endif | |
119 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
120 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
121 | ||
d1712369 KG |
122 | #ifdef CONFIG_PHYS_64BIT |
123 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
124 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
125 | #endif | |
126 | ||
127 | /* EEPROM */ | |
128 | #define CONFIG_ID_EEPROM | |
129 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
130 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
131 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
132 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
133 | ||
134 | /* | |
135 | * DDR Setup | |
136 | */ | |
137 | #define CONFIG_VERY_BIG_RAM | |
138 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
139 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
140 | ||
141 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 142 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
143 | |
144 | #define CONFIG_DDR_SPD | |
d1712369 | 145 | |
d1712369 KG |
146 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
147 | #define SPD_EEPROM_ADDRESS1 0x51 | |
148 | #define SPD_EEPROM_ADDRESS2 0x52 | |
e02aea61 | 149 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
28a96671 | 150 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
d1712369 KG |
151 | |
152 | /* | |
153 | * Local Bus Definitions | |
154 | */ | |
155 | ||
156 | /* Set the local bus clock 1/8 of platform clock */ | |
157 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
158 | ||
159 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
160 | #ifdef CONFIG_PHYS_64BIT | |
161 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
162 | #else | |
163 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
164 | #endif | |
165 | ||
374a235d | 166 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
7ee41107 | 167 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ |
374a235d SX |
168 | | BR_PS_16 | BR_V) |
169 | #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
d1712369 KG |
170 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) |
171 | ||
172 | #define CONFIG_SYS_BR1_PRELIM \ | |
173 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
174 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
175 | ||
d1712369 KG |
176 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
177 | #ifdef CONFIG_PHYS_64BIT | |
178 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
179 | #else | |
180 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
181 | #endif | |
182 | ||
183 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
184 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
185 | ||
186 | #define PIXIS_LBMAP_SWITCH 7 | |
187 | #define PIXIS_LBMAP_MASK 0xf0 | |
188 | #define PIXIS_LBMAP_SHIFT 4 | |
189 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
190 | ||
191 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
192 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
193 | ||
194 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
195 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
196 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
197 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
198 | ||
14d0a02a | 199 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 | 200 | |
2a9fab82 SX |
201 | #if defined(CONFIG_RAMBOOT_PBL) |
202 | #define CONFIG_SYS_RAMBOOT | |
203 | #endif | |
204 | ||
e02aea61 | 205 | /* Nand Flash */ |
e02aea61 KG |
206 | #ifdef CONFIG_NAND_FSL_ELBC |
207 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
208 | #ifdef CONFIG_PHYS_64BIT | |
209 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
210 | #else | |
211 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
212 | #endif | |
213 | ||
214 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
215 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
e02aea61 KG |
216 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
217 | ||
218 | /* NAND flash config */ | |
219 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
220 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
221 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
222 | | BR_MS_FCM /* MSEL = FCM */ \ | |
223 | | BR_V) /* valid */ | |
224 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
225 | | OR_FCM_PGS /* Large Page*/ \ | |
226 | | OR_FCM_CSCT \ | |
227 | | OR_FCM_CST \ | |
228 | | OR_FCM_CHT \ | |
229 | | OR_FCM_SCY_1 \ | |
230 | | OR_FCM_TRLX \ | |
231 | | OR_FCM_EHTR) | |
232 | ||
374a235d SX |
233 | #ifdef CONFIG_NAND |
234 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
235 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
236 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
237 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
238 | #else | |
239 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
240 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
241 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
242 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
243 | #endif | |
374a235d SX |
244 | #else |
245 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
246 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
c6d33901 | 247 | #endif /* CONFIG_NAND_FSL_ELBC */ |
e02aea61 | 248 | |
d1712369 KG |
249 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
250 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
251 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
252 | ||
d1712369 KG |
253 | #define CONFIG_HWCONFIG |
254 | ||
255 | /* define to use L1 as initial stack */ | |
256 | #define CONFIG_L1_INIT_RAM | |
257 | #define CONFIG_SYS_INIT_RAM_LOCK | |
258 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
259 | #ifdef CONFIG_PHYS_64BIT | |
260 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
261 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
262 | /* The assembler doesn't like typecast */ | |
263 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
264 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
265 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
266 | #else | |
267 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
268 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
269 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
270 | #endif | |
553f0982 | 271 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
d1712369 | 272 | |
25ddd1fb | 273 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d1712369 KG |
274 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
275 | ||
9307cbab | 276 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
d1712369 KG |
277 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
278 | ||
279 | /* Serial Port - controlled on board with jumper J8 | |
280 | * open - index 2 | |
281 | * shorted - index 1 | |
282 | */ | |
d1712369 KG |
283 | #define CONFIG_SYS_NS16550_SERIAL |
284 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
285 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
286 | ||
287 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
288 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
289 | ||
290 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
291 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
292 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
293 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
294 | ||
d1712369 | 295 | /* I2C */ |
00f792e0 HS |
296 | #define CONFIG_SYS_I2C |
297 | #define CONFIG_SYS_I2C_FSL | |
298 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
299 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
300 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
301 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
302 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
303 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
d1712369 KG |
304 | |
305 | /* | |
306 | * RapidIO | |
307 | */ | |
a09b9b68 | 308 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
d1712369 | 309 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 310 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
d1712369 | 311 | #else |
a09b9b68 | 312 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
d1712369 | 313 | #endif |
a09b9b68 | 314 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 315 | |
a09b9b68 | 316 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
d1712369 | 317 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 318 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
d1712369 | 319 | #else |
a09b9b68 | 320 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
d1712369 | 321 | #endif |
a09b9b68 | 322 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 323 | |
5ffa88ec LG |
324 | /* |
325 | * for slave u-boot IMAGE instored in master memory space, | |
326 | * PHYS must be aligned based on the SIZE | |
327 | */ | |
e4911815 LG |
328 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
329 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
330 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
331 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
3f1af81b | 332 | /* |
ff65f126 | 333 | * for slave UCODE and ENV instored in master memory space, |
3f1af81b LG |
334 | * PHYS must be aligned based on the SIZE |
335 | */ | |
e4911815 | 336 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
b5f7c873 LG |
337 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
338 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
ff65f126 | 339 | |
5056c8e0 | 340 | /* slave core release by master*/ |
b5f7c873 LG |
341 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
342 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
5ffa88ec | 343 | |
292dc6c5 | 344 | /* |
461632bd | 345 | * SRIO_PCIE_BOOT - SLAVE |
292dc6c5 | 346 | */ |
461632bd LG |
347 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
348 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
349 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
350 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
292dc6c5 LG |
351 | #endif |
352 | ||
2dd3095d SX |
353 | /* |
354 | * eSPI - Enhanced SPI | |
355 | */ | |
2dd3095d | 356 | |
d1712369 KG |
357 | /* |
358 | * General PCI | |
359 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
360 | */ | |
361 | ||
362 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
363 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
d1712369 | 364 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
d1712369 | 365 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
d1712369 | 366 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
d1712369 KG |
367 | |
368 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
369 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
d1712369 | 370 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
d1712369 | 371 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
d1712369 | 372 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
d1712369 KG |
373 | |
374 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
02bb4989 | 375 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
d1712369 | 376 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull |
d1712369 | 377 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
d1712369 | 378 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
d1712369 | 379 | |
1bf8e9fd | 380 | /* controller 4, Base address 203000 */ |
1bf8e9fd | 381 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull |
1bf8e9fd | 382 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
1bf8e9fd | 383 | |
d1712369 KG |
384 | /* Qman/Bman */ |
385 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
386 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
387 | #ifdef CONFIG_PHYS_64BIT | |
388 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
389 | #else | |
390 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
391 | #endif | |
392 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
393 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
394 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
395 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
396 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
397 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
398 | CONFIG_SYS_BMAN_CENA_SIZE) | |
399 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
400 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
d1712369 KG |
401 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
402 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
403 | #ifdef CONFIG_PHYS_64BIT | |
404 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
405 | #else | |
406 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
407 | #endif | |
408 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
409 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
410 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
411 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
412 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
413 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
414 | CONFIG_SYS_QMAN_CENA_SIZE) | |
415 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
416 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
d1712369 KG |
417 | |
418 | #define CONFIG_SYS_DPAA_FMAN | |
419 | #define CONFIG_SYS_DPAA_PME | |
420 | /* Default address of microcode for the Linux Fman driver */ | |
ffadc441 TT |
421 | #if defined(CONFIG_SPIFLASH) |
422 | /* | |
423 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
424 | * env, so we got 0x110000. | |
425 | */ | |
dcf1d774 | 426 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
ffadc441 TT |
427 | #elif defined(CONFIG_SDCARD) |
428 | /* | |
429 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
e222b1f3 PK |
430 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
431 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
ffadc441 | 432 | */ |
dcf1d774 | 433 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
ffadc441 | 434 | #elif defined(CONFIG_NAND) |
dcf1d774 | 435 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 436 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
292dc6c5 LG |
437 | /* |
438 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
439 | * in two corenet boards, slave's ucode could be stored in master's memory | |
440 | * space, the address can be mapped from slave TLB->slave LAW-> | |
461632bd LG |
441 | * slave SRIO or PCIE outbound window->master inbound window-> |
442 | * master LAW->the ucode address in master's memory space. | |
292dc6c5 | 443 | */ |
dcf1d774 | 444 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
d1712369 | 445 | #else |
dcf1d774 | 446 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
d1712369 | 447 | #endif |
f2717b47 TT |
448 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
449 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
d1712369 KG |
450 | |
451 | #ifdef CONFIG_SYS_DPAA_FMAN | |
2915609a AF |
452 | #define CONFIG_PHYLIB_10G |
453 | #define CONFIG_PHY_VITESSE | |
454 | #define CONFIG_PHY_TERANETICS | |
d1712369 KG |
455 | #endif |
456 | ||
457 | #ifdef CONFIG_PCI | |
7bf7edd4 HZ |
458 | #if !defined(CONFIG_DM_PCI) |
459 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
842033e6 | 460 | #define CONFIG_PCI_INDIRECT_BRIDGE |
7bf7edd4 HZ |
461 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
462 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
463 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
464 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
465 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
466 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
467 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
468 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
469 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
470 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
471 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
472 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
473 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
474 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
475 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
476 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
477 | #endif | |
d1712369 | 478 | |
d1712369 | 479 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
d1712369 KG |
480 | #endif /* CONFIG_PCI */ |
481 | ||
482 | /* SATA */ | |
483 | #ifdef CONFIG_FSL_SATA_V2 | |
d1712369 KG |
484 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
485 | #define CONFIG_SATA1 | |
486 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
487 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
488 | #define CONFIG_SATA2 | |
489 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
490 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
491 | ||
492 | #define CONFIG_LBA48 | |
d1712369 KG |
493 | #endif |
494 | ||
495 | #ifdef CONFIG_FMAN_ENET | |
496 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
497 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
498 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
499 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
500 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
501 | ||
d1712369 KG |
502 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c |
503 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
504 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
505 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
506 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
d1712369 KG |
507 | |
508 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
d1712369 | 509 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
d1712369 KG |
510 | #endif |
511 | ||
512 | /* | |
513 | * Environment | |
514 | */ | |
d1712369 KG |
515 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
516 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
517 | ||
d1712369 KG |
518 | /* |
519 | * USB | |
520 | */ | |
3d7506fa | 521 | #define CONFIG_HAS_FSL_DR_USB |
522 | #define CONFIG_HAS_FSL_MPH_USB | |
523 | ||
524 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
d1712369 KG |
525 | #define CONFIG_USB_EHCI_FSL |
526 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3d7506fa | 527 | #endif |
d1712369 | 528 | |
d1712369 | 529 | #ifdef CONFIG_MMC |
d1712369 KG |
530 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
531 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
d1712369 KG |
532 | #endif |
533 | ||
534 | /* | |
535 | * Miscellaneous configurable options | |
536 | */ | |
d1712369 | 537 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
d1712369 KG |
538 | |
539 | /* | |
540 | * For booting Linux, the board info and command line data | |
a832ac41 | 541 | * have to be in the first 64 MB of memory, since this is |
d1712369 KG |
542 | * the maximum mapped by the Linux kernel during initialization. |
543 | */ | |
a832ac41 KG |
544 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
545 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d1712369 | 546 | |
d1712369 KG |
547 | #ifdef CONFIG_CMD_KGDB |
548 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
d1712369 KG |
549 | #endif |
550 | ||
551 | /* | |
552 | * Environment Configuration | |
553 | */ | |
8b3637c6 | 554 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 555 | #define CONFIG_BOOTFILE "uImage" |
d1712369 KG |
556 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
557 | ||
558 | /* default location for tftp and bootm */ | |
559 | #define CONFIG_LOADADDR 1000000 | |
560 | ||
529fb062 | 561 | #ifdef CONFIG_TARGET_P4080DS |
68d4230c RM |
562 | #define __USB_PHY_TYPE ulpi |
563 | #else | |
564 | #define __USB_PHY_TYPE utmi | |
565 | #endif | |
566 | ||
d1712369 | 567 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
c2b3b640 | 568 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
68d4230c | 569 | "bank_intlv=cs0_cs1;" \ |
55964bb6 | 570 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ |
571 | "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
d1712369 | 572 | "netdev=eth0\0" \ |
5368c55d MV |
573 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
574 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
c2b3b640 EM |
575 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
576 | "protect off $ubootaddr +$filesize && " \ | |
577 | "erase $ubootaddr +$filesize && " \ | |
578 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
579 | "protect on $ubootaddr +$filesize && " \ | |
580 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
581 | "consoledev=ttyS0\0" \ |
582 | "ramdiskaddr=2000000\0" \ | |
583 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
b24a4f62 | 584 | "fdtaddr=1e00000\0" \ |
d1712369 | 585 | "fdtfile=p4080ds/p4080ds.dtb\0" \ |
3246584d | 586 | "bdev=sda3\0" |
d1712369 KG |
587 | |
588 | #define CONFIG_HDBOOT \ | |
589 | "setenv bootargs root=/dev/$bdev rw " \ | |
590 | "console=$consoledev,$baudrate $othbootargs;" \ | |
591 | "tftp $loadaddr $bootfile;" \ | |
592 | "tftp $fdtaddr $fdtfile;" \ | |
593 | "bootm $loadaddr - $fdtaddr" | |
594 | ||
595 | #define CONFIG_NFSBOOTCOMMAND \ | |
596 | "setenv bootargs root=/dev/nfs rw " \ | |
597 | "nfsroot=$serverip:$rootpath " \ | |
598 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
599 | "console=$consoledev,$baudrate $othbootargs;" \ | |
600 | "tftp $loadaddr $bootfile;" \ | |
601 | "tftp $fdtaddr $fdtfile;" \ | |
602 | "bootm $loadaddr - $fdtaddr" | |
603 | ||
604 | #define CONFIG_RAMBOOTCOMMAND \ | |
605 | "setenv bootargs root=/dev/ram rw " \ | |
606 | "console=$consoledev,$baudrate $othbootargs;" \ | |
607 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
608 | "tftp $loadaddr $bootfile;" \ | |
609 | "tftp $fdtaddr $fdtfile;" \ | |
610 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
611 | ||
612 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
613 | ||
7065b7d4 | 614 | #include <asm/fsl_secure_boot.h> |
7065b7d4 | 615 | |
d1712369 | 616 | #endif /* __CONFIG_H */ |