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1 | /* |
2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Corenet DS style board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #include "../board/freescale/common/ics307_clk.h" | |
30 | ||
31 | /* High Level Configuration Options */ | |
32 | #define CONFIG_BOOKE | |
33 | #define CONFIG_E500 /* BOOKE e500 family */ | |
34 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
35 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
36 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
37 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
38 | #define CONFIG_MP /* support multiple processors */ | |
39 | ||
40 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
41 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
42 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
43 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
44 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
45 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
46 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
47 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
48 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
49 | #define CONFIG_SYS_HAS_SERDES /* has SERDES */ | |
50 | ||
51 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
52 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
53 | ||
54 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
55 | ||
56 | #define CONFIG_ENV_OVERWRITE | |
57 | ||
58 | #ifdef CONFIG_SYS_NO_FLASH | |
59 | #define CONFIG_ENV_IS_NOWHERE | |
60 | #else | |
61 | #define CONFIG_ENV_IS_IN_FLASH | |
62 | #define CONFIG_FLASH_CFI_DRIVER | |
63 | #define CONFIG_SYS_FLASH_CFI | |
64 | #endif | |
65 | ||
66 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
67 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ | |
68 | ||
69 | /* | |
70 | * These can be toggled for performance analysis, otherwise use default. | |
71 | */ | |
72 | #define CONFIG_SYS_CACHE_STASHING | |
73 | #define CONFIG_BACKSIDE_L2_CACHE | |
74 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
75 | #define CONFIG_BTB /* toggle branch predition */ | |
2d941de9 | 76 | /*#define CONFIG_DDR_ECC*/ |
d1712369 KG |
77 | #ifdef CONFIG_DDR_ECC |
78 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
79 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
80 | #endif | |
81 | ||
82 | #define CONFIG_ENABLE_36BIT_PHYS | |
83 | ||
84 | #ifdef CONFIG_PHYS_64BIT | |
85 | #define CONFIG_ADDR_MAP | |
86 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
87 | #endif | |
88 | ||
4672e1ea | 89 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
90 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
91 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
92 | #define CONFIG_SYS_ALT_MEMTEST | |
93 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
94 | ||
95 | /* | |
96 | * Base addresses -- Note these are effective addresses where the | |
97 | * actual resources get mapped (not physical addresses) | |
98 | */ | |
99 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ | |
100 | #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ | |
101 | #ifdef CONFIG_PHYS_64BIT | |
102 | #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ | |
103 | #else | |
104 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
105 | #endif | |
106 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
107 | ||
108 | #ifdef CONFIG_PHYS_64BIT | |
109 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
110 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
111 | #endif | |
112 | ||
113 | /* EEPROM */ | |
114 | #define CONFIG_ID_EEPROM | |
115 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
116 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
117 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
118 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
119 | ||
120 | /* | |
121 | * DDR Setup | |
122 | */ | |
123 | #define CONFIG_VERY_BIG_RAM | |
124 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
126 | ||
127 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 128 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
129 | |
130 | #define CONFIG_DDR_SPD | |
131 | #define CONFIG_FSL_DDR3 | |
132 | ||
133 | #ifdef CONFIG_DDR_SPD | |
134 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
135 | #define SPD_EEPROM_ADDRESS1 0x51 | |
136 | #define SPD_EEPROM_ADDRESS2 0x52 | |
137 | #else | |
138 | #define CONFIG_SYS_SDRAM_SIZE 4096 | |
139 | ||
140 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
141 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f | |
142 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
143 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 | |
144 | #define CONFIG_SYS_DDR_TIMING_3 0x01031000 | |
145 | #define CONFIG_SYS_DDR_TIMING_0 0x55440804 | |
146 | #define CONFIG_SYS_DDR_TIMING_1 0x74713a66 | |
147 | #define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b | |
148 | #define CONFIG_SYS_DDR_MODE_1 0x00421850 | |
149 | #define CONFIG_SYS_DDR_MODE_2 0x00100000 | |
150 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 | |
151 | #define CONFIG_SYS_DDR_INTERVAL 0x10400100 | |
152 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
153 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
154 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
155 | #define CONFIG_SYS_DDR_TIMING_5 0x03401500 | |
156 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
157 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 | |
158 | #define CONFIG_SYS_DDR_CONTROL 0xc7048000 | |
159 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 | |
160 | #define CONFIG_SYS_DDR_CDR1 0x00000000 | |
161 | #define CONFIG_SYS_DDR_CDR2 0x00000000 | |
162 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
163 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
164 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
165 | #define CONFIG_SYS_DDR_DEBUG_18 0x40100400 | |
166 | ||
167 | #define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf | |
168 | #define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff | |
169 | #define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG | |
170 | #define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG | |
171 | #define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 | |
172 | #define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 | |
173 | #define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 | |
174 | #define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 | |
175 | #define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 | |
176 | #define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 | |
177 | #define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL | |
178 | #define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL | |
179 | #define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT | |
180 | #define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL | |
181 | #define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 | |
182 | #define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 | |
183 | #define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL | |
184 | #define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL | |
185 | #define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL | |
186 | #define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 | |
187 | #define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 | |
188 | #define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 | |
189 | #define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN | |
190 | #define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS | |
191 | #define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE | |
192 | #define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 | |
193 | ||
194 | #endif | |
195 | ||
196 | /* | |
197 | * Local Bus Definitions | |
198 | */ | |
199 | ||
200 | /* Set the local bus clock 1/8 of platform clock */ | |
201 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
202 | ||
203 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
204 | #ifdef CONFIG_PHYS_64BIT | |
205 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
206 | #else | |
207 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
208 | #endif | |
209 | ||
210 | #define CONFIG_SYS_BR0_PRELIM \ | |
211 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ | |
212 | BR_PS_16 | BR_V) | |
213 | #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
214 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
215 | ||
216 | #define CONFIG_SYS_BR1_PRELIM \ | |
217 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
218 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
219 | ||
220 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ | |
221 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
222 | #ifdef CONFIG_PHYS_64BIT | |
223 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
224 | #else | |
225 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
226 | #endif | |
227 | ||
228 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
229 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
230 | ||
231 | #define PIXIS_LBMAP_SWITCH 7 | |
232 | #define PIXIS_LBMAP_MASK 0xf0 | |
233 | #define PIXIS_LBMAP_SHIFT 4 | |
234 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
235 | ||
236 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
237 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
238 | ||
239 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
240 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
241 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
242 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
243 | ||
14d0a02a | 244 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 KG |
245 | |
246 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
247 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
248 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
249 | ||
250 | #define CONFIG_BOARD_EARLY_INIT_F | |
251 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
252 | #define CONFIG_MISC_INIT_R | |
253 | ||
254 | #define CONFIG_HWCONFIG | |
255 | ||
256 | /* define to use L1 as initial stack */ | |
257 | #define CONFIG_L1_INIT_RAM | |
258 | #define CONFIG_SYS_INIT_RAM_LOCK | |
259 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
260 | #ifdef CONFIG_PHYS_64BIT | |
261 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
262 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
263 | /* The assembler doesn't like typecast */ | |
264 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
265 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
266 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
267 | #else | |
268 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
269 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
270 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
271 | #endif | |
272 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
273 | ||
274 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
275 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
276 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
277 | ||
278 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
279 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
280 | ||
281 | /* Serial Port - controlled on board with jumper J8 | |
282 | * open - index 2 | |
283 | * shorted - index 1 | |
284 | */ | |
285 | #define CONFIG_CONS_INDEX 1 | |
286 | #define CONFIG_SYS_NS16550 | |
287 | #define CONFIG_SYS_NS16550_SERIAL | |
288 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
289 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
290 | ||
291 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
292 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
293 | ||
294 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
295 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
296 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
297 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
298 | ||
299 | /* Use the HUSH parser */ | |
300 | #define CONFIG_SYS_HUSH_PARSER | |
301 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
302 | ||
303 | /* pass open firmware flat tree */ | |
304 | #define CONFIG_OF_LIBFDT | |
305 | #define CONFIG_OF_BOARD_SETUP | |
306 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
307 | ||
308 | /* new uImage format support */ | |
309 | #define CONFIG_FIT | |
310 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
311 | ||
312 | /* I2C */ | |
313 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
314 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
315 | #define CONFIG_I2C_MULTI_BUS | |
316 | #define CONFIG_I2C_CMD_TREE | |
317 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
318 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
319 | #define CONFIG_SYS_I2C_OFFSET 0x118000 | |
320 | #define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
321 | ||
322 | /* | |
323 | * RapidIO | |
324 | */ | |
325 | #define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 | |
326 | #ifdef CONFIG_PHYS_64BIT | |
327 | #define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull | |
328 | #else | |
329 | #define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 | |
330 | #endif | |
331 | #define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ | |
332 | ||
333 | #define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 | |
334 | #ifdef CONFIG_PHYS_64BIT | |
335 | #define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull | |
336 | #else | |
337 | #define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 | |
338 | #endif | |
339 | #define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ | |
340 | ||
341 | /* | |
342 | * General PCI | |
343 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
344 | */ | |
345 | ||
346 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
347 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
348 | #ifdef CONFIG_PHYS_64BIT | |
349 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
350 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
351 | #else | |
352 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
353 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
354 | #endif | |
355 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
356 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
357 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
358 | #ifdef CONFIG_PHYS_64BIT | |
359 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
360 | #else | |
361 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
362 | #endif | |
363 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
364 | ||
365 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
366 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
367 | #ifdef CONFIG_PHYS_64BIT | |
368 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
369 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
370 | #else | |
371 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
372 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
373 | #endif | |
374 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
375 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
376 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
377 | #ifdef CONFIG_PHYS_64BIT | |
378 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
379 | #else | |
380 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
381 | #endif | |
382 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
383 | ||
384 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
385 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 | |
386 | #ifdef CONFIG_PHYS_64BIT | |
387 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
388 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
389 | #else | |
390 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
391 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
392 | #endif | |
393 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
394 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
395 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
396 | #ifdef CONFIG_PHYS_64BIT | |
397 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
398 | #else | |
399 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
400 | #endif | |
401 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
402 | ||
1bf8e9fd KG |
403 | /* controller 4, Base address 203000 */ |
404 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
405 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
406 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
407 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
408 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
409 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
410 | ||
d1712369 KG |
411 | /* Qman/Bman */ |
412 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
413 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
414 | #ifdef CONFIG_PHYS_64BIT | |
415 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
416 | #else | |
417 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
418 | #endif | |
419 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
420 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
421 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
422 | #ifdef CONFIG_PHYS_64BIT | |
423 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
424 | #else | |
425 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
426 | #endif | |
427 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
428 | ||
429 | #define CONFIG_SYS_DPAA_FMAN | |
430 | #define CONFIG_SYS_DPAA_PME | |
431 | /* Default address of microcode for the Linux Fman driver */ | |
432 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 | |
433 | #ifdef CONFIG_PHYS_64BIT | |
434 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL | |
435 | #else | |
436 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR | |
437 | #endif | |
438 | ||
439 | #ifdef CONFIG_SYS_DPAA_FMAN | |
440 | #define CONFIG_FMAN_ENET | |
441 | #endif | |
442 | ||
443 | #ifdef CONFIG_PCI | |
444 | ||
445 | /*PCIE video card used*/ | |
446 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT | |
447 | ||
448 | /* video */ | |
449 | #define CONFIG_VIDEO | |
450 | ||
451 | #ifdef CONFIG_VIDEO | |
452 | #define CONFIG_BIOSEMU | |
453 | #define CONFIG_CFB_CONSOLE | |
454 | #define CONFIG_VIDEO_SW_CURSOR | |
455 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
456 | #define CONFIG_ATI_RADEON_FB | |
457 | #define CONFIG_VIDEO_LOGO | |
458 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
459 | #endif | |
460 | ||
461 | #define CONFIG_NET_MULTI | |
462 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
463 | #define CONFIG_E1000 | |
464 | ||
465 | #ifndef CONFIG_PCI_PNP | |
466 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS | |
467 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
468 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
469 | #endif | |
470 | ||
471 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
472 | #define CONFIG_DOS_PARTITION | |
473 | #endif /* CONFIG_PCI */ | |
474 | ||
475 | /* SATA */ | |
476 | #ifdef CONFIG_FSL_SATA_V2 | |
477 | #define CONFIG_LIBATA | |
478 | #define CONFIG_FSL_SATA | |
479 | ||
480 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
481 | #define CONFIG_SATA1 | |
482 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
483 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
484 | #define CONFIG_SATA2 | |
485 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
486 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
487 | ||
488 | #define CONFIG_LBA48 | |
489 | #define CONFIG_CMD_SATA | |
490 | #define CONFIG_DOS_PARTITION | |
491 | #define CONFIG_CMD_EXT2 | |
492 | #endif | |
493 | ||
494 | #ifdef CONFIG_FMAN_ENET | |
495 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
496 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
497 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
498 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
499 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
500 | ||
501 | #if (CONFIG_SYS_NUM_FMAN == 2) | |
502 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c | |
503 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
504 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
505 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
506 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
507 | #endif | |
508 | ||
509 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
510 | #define CONFIG_MII /* MII PHY management */ | |
511 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
512 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
513 | #endif | |
514 | ||
515 | /* | |
516 | * Environment | |
517 | */ | |
518 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
519 | #define CONFIG_ENV_SIZE 0x2000 | |
520 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
521 | ||
522 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
523 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
524 | ||
525 | /* | |
526 | * Command line configuration. | |
527 | */ | |
528 | #include <config_cmd_default.h> | |
529 | ||
530 | #define CONFIG_CMD_ELF | |
531 | #define CONFIG_CMD_ERRATA | |
532 | #define CONFIG_CMD_IRQ | |
533 | #define CONFIG_CMD_I2C | |
534 | #define CONFIG_CMD_MII | |
535 | #define CONFIG_CMD_PING | |
536 | #define CONFIG_CMD_SETEXPR | |
537 | ||
538 | #ifdef CONFIG_PCI | |
539 | #define CONFIG_CMD_PCI | |
540 | #define CONFIG_CMD_NET | |
541 | #endif | |
542 | ||
543 | /* | |
544 | * USB | |
545 | */ | |
546 | #define CONFIG_CMD_USB | |
547 | #define CONFIG_USB_STORAGE | |
548 | #define CONFIG_USB_EHCI | |
549 | #define CONFIG_USB_EHCI_FSL | |
550 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
551 | #define CONFIG_CMD_EXT2 | |
552 | ||
553 | #define CONFIG_MMC | |
554 | ||
555 | #ifdef CONFIG_MMC | |
556 | #define CONFIG_FSL_ESDHC | |
557 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
558 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
559 | #define CONFIG_CMD_MMC | |
560 | #define CONFIG_GENERIC_MMC | |
561 | #define CONFIG_CMD_EXT2 | |
562 | #define CONFIG_CMD_FAT | |
563 | #define CONFIG_DOS_PARTITION | |
564 | #endif | |
565 | ||
566 | /* | |
567 | * Miscellaneous configurable options | |
568 | */ | |
569 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
570 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
571 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
572 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
573 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
574 | #ifdef CONFIG_CMD_KGDB | |
575 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
576 | #else | |
577 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
578 | #endif | |
579 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
580 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
581 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
582 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
583 | ||
584 | /* | |
585 | * For booting Linux, the board info and command line data | |
586 | * have to be in the first 16 MB of memory, since this is | |
587 | * the maximum mapped by the Linux kernel during initialization. | |
588 | */ | |
589 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
590 | ||
d1712369 KG |
591 | #ifdef CONFIG_CMD_KGDB |
592 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
593 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
594 | #endif | |
595 | ||
596 | /* | |
597 | * Environment Configuration | |
598 | */ | |
599 | #define CONFIG_ROOTPATH /opt/nfsroot | |
600 | #define CONFIG_BOOTFILE uImage | |
601 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
602 | ||
603 | /* default location for tftp and bootm */ | |
604 | #define CONFIG_LOADADDR 1000000 | |
605 | ||
606 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
607 | ||
608 | #define CONFIG_BAUDRATE 115200 | |
609 | ||
610 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
c2b3b640 EM |
611 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
612 | "bank_intlv=cs0_cs1\0" \ | |
d1712369 KG |
613 | "netdev=eth0\0" \ |
614 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
14d0a02a | 615 | "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ |
c2b3b640 EM |
616 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
617 | "protect off $ubootaddr +$filesize && " \ | |
618 | "erase $ubootaddr +$filesize && " \ | |
619 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
620 | "protect on $ubootaddr +$filesize && " \ | |
621 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
622 | "consoledev=ttyS0\0" \ |
623 | "ramdiskaddr=2000000\0" \ | |
624 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
625 | "fdtaddr=c00000\0" \ | |
626 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
627 | "bdev=sda3\0" \ | |
628 | "c=ffe\0" \ | |
629 | "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" | |
630 | ||
631 | #define CONFIG_HDBOOT \ | |
632 | "setenv bootargs root=/dev/$bdev rw " \ | |
633 | "console=$consoledev,$baudrate $othbootargs;" \ | |
634 | "tftp $loadaddr $bootfile;" \ | |
635 | "tftp $fdtaddr $fdtfile;" \ | |
636 | "bootm $loadaddr - $fdtaddr" | |
637 | ||
638 | #define CONFIG_NFSBOOTCOMMAND \ | |
639 | "setenv bootargs root=/dev/nfs rw " \ | |
640 | "nfsroot=$serverip:$rootpath " \ | |
641 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
642 | "console=$consoledev,$baudrate $othbootargs;" \ | |
643 | "tftp $loadaddr $bootfile;" \ | |
644 | "tftp $fdtaddr $fdtfile;" \ | |
645 | "bootm $loadaddr - $fdtaddr" | |
646 | ||
647 | #define CONFIG_RAMBOOTCOMMAND \ | |
648 | "setenv bootargs root=/dev/ram rw " \ | |
649 | "console=$consoledev,$baudrate $othbootargs;" \ | |
650 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
651 | "tftp $loadaddr $bootfile;" \ | |
652 | "tftp $fdtaddr $fdtfile;" \ | |
653 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
654 | ||
655 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
656 | ||
657 | #endif /* __CONFIG_H */ |