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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
b89ac72a HS |
2 | /* |
3 | * Common board functions for siemens AT91SAM9G45 based boards | |
4 | * (C) Copyright 2013 Siemens AG | |
5 | * | |
6 | * Based on: | |
7 | * U-Boot file: include/configs/at91sam9m10g45ek.h | |
8 | * (C) Copyright 2007-2008 | |
9 | * Stelian Pop <stelian@popies.net> | |
10 | * Lead Tech Design <www.leadtechdesign.com> | |
b89ac72a HS |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | #include <asm/hardware.h> | |
fd45a0d1 | 17 | #include <linux/sizes.h> |
b89ac72a | 18 | |
b89ac72a HS |
19 | /* |
20 | * Warning: changing CONFIG_SYS_TEXT_BASE requires | |
21 | * adapting the initial boot program. | |
22 | * Since the linker has to swallow that define, we must use a pure | |
23 | * hex number here! | |
24 | */ | |
25 | ||
b89ac72a HS |
26 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
27 | ||
28 | /* ARM asynchronous clock */ | |
29 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
30 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ | |
b89ac72a | 31 | |
b89ac72a HS |
32 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
33 | #define CONFIG_SETUP_MEMORY_TAGS | |
34 | #define CONFIG_INITRD_TAG | |
b89ac72a | 35 | |
b89ac72a HS |
36 | /* general purpose I/O */ |
37 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ | |
b89ac72a HS |
38 | #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ |
39 | ||
40 | /* serial console */ | |
b89ac72a HS |
41 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
42 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
43 | ||
44 | /* LED */ | |
45 | #define CONFIG_AT91_LED | |
46 | #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ | |
47 | #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ | |
48 | ||
b89ac72a HS |
49 | |
50 | /* | |
51 | * BOOTP options | |
52 | */ | |
53 | #define CONFIG_BOOTP_BOOTFILESIZE | |
b89ac72a | 54 | |
b89ac72a | 55 | /* SDRAM */ |
b89ac72a HS |
56 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 |
57 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 | |
58 | ||
59 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
72fa5893 | 60 | (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) |
b89ac72a | 61 | |
b89ac72a HS |
62 | /* NAND flash */ |
63 | #ifdef CONFIG_CMD_NAND | |
b89ac72a HS |
64 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
65 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 | |
66 | #define CONFIG_SYS_NAND_DBW_8 | |
67 | /* our ALE is AD21 */ | |
68 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
69 | /* our CLE is AD22 */ | |
70 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
71 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
a5f8ccae | 72 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 |
d76f093f | 73 | #define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT |
b89ac72a HS |
74 | #endif |
75 | ||
76 | /* Ethernet */ | |
77 | #define CONFIG_MACB | |
78 | #define CONFIG_RMII | |
79 | #define CONFIG_NET_RETRY_COUNT 20 | |
80 | #define CONFIG_AT91_WANTS_COMMON_PHY | |
81 | ||
e11793bc | 82 | /* DFU class support */ |
e11793bc HS |
83 | #define DFU_MANIFEST_POLL_TIMEOUT 25000 |
84 | ||
b89ac72a | 85 | /* bootstrap + u-boot + env in nandflash */ |
b89ac72a HS |
86 | |
87 | #define CONFIG_BOOTCOMMAND \ | |
88 | "nand read 0x70000000 0x200000 0x300000;" \ | |
89 | "bootm 0x70000000" | |
b89ac72a | 90 | |
b89ac72a HS |
91 | /* |
92 | * Size of malloc() pool | |
93 | */ | |
94 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ | |
fd45a0d1 HS |
95 | SZ_4M, 0x1000) |
96 | ||
5b15fd98 | 97 | /* Defines for SPL */ |
fd45a0d1 HS |
98 | #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) |
99 | #define CONFIG_SPL_STACK (SZ_16K) | |
5b15fd98 HS |
100 | |
101 | #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE | |
fd45a0d1 | 102 | #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) |
5b15fd98 | 103 | |
5b15fd98 HS |
104 | #define CONFIG_SPL_NAND_RAW_ONLY |
105 | #define CONFIG_SPL_NAND_SOFTECC | |
106 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 | |
107 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 | |
108 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
109 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
110 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
111 | ||
fd45a0d1 HS |
112 | #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K |
113 | #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) | |
5b15fd98 HS |
114 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ |
115 | CONFIG_SYS_NAND_PAGE_SIZE) | |
116 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
117 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
118 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
119 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
120 | #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ | |
121 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
122 | 56, 57, 58, 59, 60, 61, 62, 63, } | |
123 | ||
124 | #define CONFIG_SPL_ATMEL_SIZE | |
125 | #define CONFIG_SYS_MASTER_CLOCK 132096000 | |
126 | #define AT91_PLL_LOCK_TIMEOUT 1000000 | |
127 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 | |
128 | #define CONFIG_SYS_MCKR 0x1301 | |
129 | #define CONFIG_SYS_MCKR_CSS 0x1302 | |
130 | ||
fc89afba SR |
131 | #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS |
132 | #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO | |
133 | ||
b89ac72a | 134 | #endif |