[people/ms/u-boot.git] / include / configs / cpci5200.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+

 */

/*************************************************************************
 * (c) 2005 esd gmbh Hannover
 *
 *
 * from IceCube.h file
 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
 *
 *************************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
#define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported 	  */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#if 1
#define CONFIG_PCI		1
#if 1
#define CONFIG_PCI_PNP		1
#endif
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_MII
#if 0				/* test-only !!! */
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/* USB */
#if 0
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_DATE

#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
#   define CONFIG_SYS_LOWBOOT		1
#   define CONFIG_SYS_LOWBOOT08	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome to esd CPU CPCI/5200;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=eth0\0" \
	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
	"loadaddr=01000000\0" \
	"serverip=192.168.2.99\0" \
	"gatewayip=10.0.0.79\0" \
	"user=mu\0" \
	"target=cpci5200.esd\0" \
	"script=cpci5200.bat\0" \
	"image=/tftpboot/vxWorks_cpci5200\0" \
	"ipaddr=10.0.13.196\0" \
	"netmask=255.255.0.0\0" \
	""

#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"

#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfd010000
#define CONFIG_SYS_NVRAM_SIZE		32*1024

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
/*
 * Flash configuration
 */

#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant	     */
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x02000000
#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	128

#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection	     */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/*
 * Environment settings
 */
#if 1				/* test-only */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1
#else
#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
				   /* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE	1
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_UDP_CHECKSUM	1

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00

#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS1_START		0xfd000000
#define CONFIG_SYS_CS1_SIZE		0x00010000
#define CONFIG_SYS_CS1_CFG		0x10101410

#define CONFIG_SYS_CS3_START		0xfd010000
#define CONFIG_SYS_CS3_SIZE		0x00010000
#define CONFIG_SYS_CS3_CFG		0x10109410

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/

#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CONFIG_SYS_ATA_STRIDE		4

/*-----------------------------------------------------------------------
 * CPLD stuff
 */
#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */

/* CPLD program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */

#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */

#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
#define JTAG_GPIO_CFG_SET	0x00000000
#define JTAG_GPIO_CFG_RESET	0x00F00000

#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TMS_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TMS_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
#define JTAG_GPIO_TCK_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
#define JTAG_GPIO_TCK_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDI_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
#define JTAG_GPIO_TDI_DDR_RESET 0x00000000

#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
#define JTAG_GPIO_TDO_EN_RESET	0x00000000
#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
#define JTAG_GPIO_TDO_DDR_SET	0x00000000
#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */

#endif				/* __CONFIG_H */
Commit	Line	Data
5e4b3361 SR	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
5e4b3361 SR	6
	7	*/
	8
	9	/*************************************************************************
	10	* (c) 2005 esd gmbh Hannover
	11	*
	12	*
	13	* from IceCube.h file
	14	* by Reinhard Arlt reinhard.arlt@esd-electronics.com
	15	*
	16	*************************************************************************/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
	21	/*
	22	* High Level Configuration Options
	23	* (easy to change)
	24	*/
	25
b2a6dfe4	26	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
5e4b3361 SR	27	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
	28	#define CONFIG_CPCI5200 1 /* ... on CPCI5200 board */
	29	#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
	30
2ae18241 WD	31	#ifndef CONFIG_SYS_TEXT_BASE
	32	#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
	33	#endif
	34
6d0f6bcf	35	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e4b3361	36
31d82672 BB	37	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	38
5e4b3361 SR	39	/*
	40	* Serial console configuration
	41	*/
	42	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	43	#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e4b3361	45
5e4b3361 SR	46	/*
	47	* PCI Mapping:
	48	* 0x40000000 - 0x4fffffff - PCI Memory
	49	* 0x50000000 - 0x50ffffff - PCI IO Space
	50	*/
	51	#if 1
	52	#define CONFIG_PCI 1
	53	#if 1
	54	#define CONFIG_PCI_PNP 1
	55	#endif
	56	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	57	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
5e4b3361 SR	58
	59	#define CONFIG_PCI_MEM_BUS 0x40000000
	60	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	61	#define CONFIG_PCI_MEM_SIZE 0x10000000
	62
	63	#define CONFIG_PCI_IO_BUS 0x50000000
	64	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	65	#define CONFIG_PCI_IO_SIZE 0x01000000
	66	#endif
63ff004c MB	67
63ff004c MB	68	#define CONFIG_MII
5e4b3361	69	#if 0 /* test-only !!! */
5e4b3361	70	#define CONFIG_EEPRO100 1
6d0f6bcf	71	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
5e4b3361 SR	72	#define CONFIG_NS8382X 1
	73	#endif
	74
5e4b3361 SR	75	/* Partitions */
	76	#define CONFIG_MAC_PARTITION
	77	#define CONFIG_DOS_PARTITION
	78
	79	/* USB */
	80	#if 0
	81	#define CONFIG_USB_OHCI
5e4b3361	82	#define CONFIG_USB_STORAGE
5e4b3361 SR	83	#endif
5e4b3361 SR	84
80ff4f99 JL	85	/*
	86	* BOOTP options
	87	*/
	88	#define CONFIG_BOOTP_BOOTFILESIZE
	89	#define CONFIG_BOOTP_BOOTPATH
	90	#define CONFIG_BOOTP_GATEWAY
	91	#define CONFIG_BOOTP_HOSTNAME
	92
	93
5e4b3361	94	/*
d794cfef	95	* Command line configuration.
5e4b3361	96	*/
d794cfef JL	97	#include <config_cmd_default.h>
	98
	99	#if defined(CONFIG_PCI)
	100	#define CONFIG_CMD_PCI
	101	#endif
	102
	103	#define CONFIG_CMD_EEPROM
	104	#define CONFIG_CMD_FAT
	105	#define CONFIG_CMD_IDE
	106	#define CONFIG_CMD_I2C
	107	#define CONFIG_CMD_BSP
	108	#define CONFIG_CMD_ELF
	109	#define CONFIG_CMD_EXT2
	110	#define CONFIG_CMD_DATE
	111
14d0a02a	112	#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	113	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	114	# define CONFIG_SYS_LOWBOOT16 1
5e4b3361	115	#endif
14d0a02a	116	#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
6d0f6bcf JCPV	117	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	118	# define CONFIG_SYS_LOWBOOT08 1
5e4b3361 SR	119	#endif
	120
	121	/*
	122	* Autobooting
	123	*/
	124	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	125
	126	#define CONFIG_PREBOOT "echo;" \
	127	"echo Welcome to esd CPU CPCI/5200;" \
	128	"echo"
	129
	130	#undef CONFIG_BOOTARGS
	131
	132	#define CONFIG_EXTRA_ENV_SETTINGS \
	133	"netdev=eth0\0" \
	134	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
	135	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
fe126d8b WD	136	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
	137	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
	138	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
5e4b3361 SR	139	"loadaddr=01000000\0" \
	140	"serverip=192.168.2.99\0" \
	141	"gatewayip=10.0.0.79\0" \
	142	"user=mu\0" \
	143	"target=cpci5200.esd\0" \
	144	"script=cpci5200.bat\0" \
	145	"image=/tftpboot/vxWorks_cpci5200\0" \
	146	"ipaddr=10.0.13.196\0" \
	147	"netmask=255.255.0.0\0" \
	148	""
	149
	150	#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
	151
5e4b3361	152	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
6d0f6bcf JCPV	153	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfd010000
6d0f6bcf JCPV	154	#define CONFIG_SYS_NVRAM_SIZE 32*1024
5e4b3361 SR	155
	156	/*
	157	* IPB Bus clocking configuration.
	158	*/
6d0f6bcf	159	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e4b3361 SR	160	/*
	161	* I2C configuration
	162	*/
	163	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	164	#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
5e4b3361	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
6d0f6bcf JCPV	167	#define CONFIG_SYS_I2C_SLAVE 0x7F
5e4b3361 SR	168
	169	/*
	170	* EEPROM configuration
	171	*/
6d0f6bcf JCPV	172	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	173	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	174	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	175	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	176	#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
5e4b3361 SR	177	/*
	178	* Flash configuration
	179	*/
	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
	182	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	183	#define CONFIG_SYS_FLASH_SIZE 0x02000000
	184	#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
	185	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
	186	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
	187	#define CONFIG_SYS_MAX_FLASH_SECT 128
5e4b3361	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
5e4b3361	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	193	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e4b3361 SR	194
	195	/*
	196	* Environment settings
	197	*/
	198	#if 1 /* test-only */
5a1aceb0	199	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	200	#define CONFIG_ENV_SIZE 0x20000
0e8d1586 JCPV	201	#define CONFIG_ENV_SECT_SIZE 0x20000
5e4b3361 SR	202	#define CONFIG_ENV_OVERWRITE 1
5e4b3361 SR	203	#else
bb1f8b4f	204	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	205	#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	206	#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
5e4b3361 SR	207	/* total size of a CAT24WC32 is 8192 bytes */
	208	#define CONFIG_ENV_OVERWRITE 1
	209	#endif
	210
	211	/*
	212	* Memory map
	213	*/
6d0f6bcf JCPV	214	#define CONFIG_SYS_MBAR 0xF0000000
	215	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	216	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e4b3361 SR	217
5e4b3361 SR	218	/* Use SRAM until RAM will be available */
6d0f6bcf	219	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	220	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
5e4b3361	221
25ddd1fb	222	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	223	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e4b3361	224
14d0a02a	225	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	226	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	227	# define CONFIG_SYS_RAMBOOT 1
5e4b3361 SR	228	#endif
5e4b3361 SR	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	231	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	232	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5e4b3361 SR	233
	234	/*
	235	* Ethernet configuration
	236	*/
	237	#define CONFIG_MPC5xxx_FEC 1
86321fc1	238	#define CONFIG_MPC5xxx_FEC_MII100
5e4b3361 SR	239	/*
	240	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	241	*/
	242	/* #define CONFIG_FEC_10MBIT 1 */
	243	#define CONFIG_PHY_ADDR 0x00
	244	#define CONFIG_UDP_CHECKSUM 1
	245
	246	/*
	247	* GPIO configuration
	248	*/
6d0f6bcf	249	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
5e4b3361 SR	250
	251	/*
	252	* Miscellaneous configurable options
	253	*/
6d0f6bcf	254	#define CONFIG_SYS_LONGHELP /* undef to save memory */
d794cfef	255	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	256	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e4b3361	257	#else
6d0f6bcf	258	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e4b3361	259	#endif
6d0f6bcf JCPV	260	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	261	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	262	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e4b3361	263
6d0f6bcf JCPV	264	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	265	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
5e4b3361	266
6d0f6bcf	267	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
5e4b3361	268
6d0f6bcf	269	#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
5e4b3361	270
6d0f6bcf	271	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	272	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	273	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	274	#endif
d794cfef JL	275
5e4b3361 SR	276	/*
	277	* Various low-level settings
	278	*/
6d0f6bcf JCPV	279	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	280	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e4b3361	281
6d0f6bcf JCPV	282	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	283	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	284	#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
5e4b3361	285
6d0f6bcf JCPV	286	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	287	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e4b3361	288
6d0f6bcf JCPV	289	#define CONFIG_SYS_CS1_START 0xfd000000
	290	#define CONFIG_SYS_CS1_SIZE 0x00010000
	291	#define CONFIG_SYS_CS1_CFG 0x10101410
5e4b3361	292
6d0f6bcf JCPV	293	#define CONFIG_SYS_CS3_START 0xfd010000
	294	#define CONFIG_SYS_CS3_SIZE 0x00010000
	295	#define CONFIG_SYS_CS3_CFG 0x10109410
5e4b3361	296
6d0f6bcf JCPV	297	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	298	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e4b3361	299
6d0f6bcf	300	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
5e4b3361 SR	301
	302	/*-----------------------------------------------------------------------
	303	* USB stuff
	304	*-----------------------------------------------------------------------
	305	*/
	306	#define CONFIG_USB_CLOCK 0x0001BBBB
	307	#define CONFIG_USB_CONFIG 0x00001000
	308
	309	/*-----------------------------------------------------------------------
	310	* IDE/ATA stuff Supports IDE harddisk
	311	*-----------------------------------------------------------------------
	312	*/
	313
	314	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	315
	316	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	317	#undef CONFIG_IDE_LED /* LED for ide not supported */
	318
	319	#define CONFIG_IDE_RESET /* reset for ide supported */
	320	#define CONFIG_IDE_PREINIT
	321
6d0f6bcf JCPV	322	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	323	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
5e4b3361	324
6d0f6bcf	325	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5e4b3361	326
6d0f6bcf	327	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
5e4b3361 SR	328
5e4b3361 SR	329	/* Offset for data I/O */
6d0f6bcf	330	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
5e4b3361 SR	331
5e4b3361 SR	332	/* Offset for normal register accesses */
6d0f6bcf	333	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
5e4b3361 SR	334
5e4b3361 SR	335	/* Offset for alternate registers */
6d0f6bcf	336	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
5e4b3361 SR	337
5e4b3361 SR	338	/* Interval between registers */
6d0f6bcf	339	#define CONFIG_SYS_ATA_STRIDE 4
5e4b3361 SR	340
	341	/*-----------------------------------------------------------------------
	342	* CPLD stuff
	343	*/
6d0f6bcf JCPV	344	#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
6d0f6bcf JCPV	345	#define CONFIG_SYS_FPGA_MAX_SIZE 321024 / 32kByte is enough for CPLD */
5e4b3361 SR	346
5e4b3361 SR	347	/* CPLD program pin configuration */
6d0f6bcf JCPV	348	#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
	349	#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
	350	#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
	351	#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
5e4b3361	352
6d0f6bcf JCPV	353	#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
	354	#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
	355	#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
	356	#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
5e4b3361	357
6d0f6bcf	358	#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
5e4b3361 SR	359	#define JTAG_GPIO_CFG_SET 0x00000000
	360	#define JTAG_GPIO_CFG_RESET 0x00F00000
	361
6d0f6bcf	362	#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	363	#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	364	#define JTAG_GPIO_TMS_EN_RESET 0x00000000
6d0f6bcf	365	#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	366	#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
	367	#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
	368
6d0f6bcf	369	#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	370	#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
5e4b3361 SR	371	#define JTAG_GPIO_TCK_EN_RESET 0x00000000
6d0f6bcf	372	#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	373	#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
	374	#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
	375
6d0f6bcf	376	#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
5e4b3361 SR	377	#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	378	#define JTAG_GPIO_TDI_EN_RESET 0x00000000
6d0f6bcf	379	#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
5e4b3361 SR	380	#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
	381	#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
	382
6d0f6bcf	383	#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
5e4b3361 SR	384	#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
5e4b3361 SR	385	#define JTAG_GPIO_TDO_EN_RESET 0x00000000
6d0f6bcf	386	#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
5e4b3361 SR	387	#define JTAG_GPIO_TDO_DDR_SET 0x00000000
	388	#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
	389
	390	#endif /* __CONFIG_H */