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d8380c9d | 1 | /* |
af4b8b4b | 2 | * CPUAT91 by (C) Copyright 2006-2010 Eric Benard |
d8380c9d TR |
3 | * eric@eukrea.com |
4 | * | |
5 | * Configuration settings for the CPUAT91 board. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
d8380c9d TR |
8 | */ |
9 | ||
af4b8b4b EB |
10 | #ifndef _CONFIG_CPUAT91_H |
11 | #define _CONFIG_CPUAT91_H | |
425de62d | 12 | |
1ace4022 | 13 | #include <linux/sizes.h> |
632f8fdf EB |
14 | |
15 | #ifdef CONFIG_RAMBOOT | |
16 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
17 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 | |
d8380c9d TR |
18 | #else |
19 | #define CONFIG_BOOTDELAY 1 | |
632f8fdf | 20 | #define CONFIG_SYS_TEXT_BASE 0 |
d8380c9d TR |
21 | #endif |
22 | ||
632f8fdf | 23 | #define AT91C_XTAL_CLOCK 18432000 |
6a372e94 | 24 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
632f8fdf EB |
25 | #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) |
26 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) | |
27 | #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) | |
d8380c9d | 28 | |
632f8fdf EB |
29 | #define CONFIG_AT91RM9200 |
30 | #define CONFIG_CPUAT91 | |
632f8fdf | 31 | #define USE_920T_MMU |
d8380c9d | 32 | |
6a372e94 AB |
33 | #include <asm/hardware.h> /* needed for port definitions */ |
34 | ||
632f8fdf EB |
35 | #define CONFIG_CMDLINE_TAG |
36 | #define CONFIG_SETUP_MEMORY_TAGS | |
37 | #define CONFIG_INITRD_TAG | |
dbbf13ba | 38 | #define CONFIG_BOARD_EARLY_INIT_F |
d8380c9d TR |
39 | |
40 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
632f8fdf | 41 | #define CONFIG_SYS_USE_MAIN_OSCILLATOR |
d8380c9d TR |
42 | /* flash */ |
43 | #define CONFIG_SYS_MC_PUIA_VAL 0x00000000 | |
44 | #define CONFIG_SYS_MC_PUP_VAL 0x00000000 | |
45 | #define CONFIG_SYS_MC_PUER_VAL 0x00000000 | |
46 | #define CONFIG_SYS_MC_ASR_VAL 0x00000000 | |
47 | #define CONFIG_SYS_MC_AASR_VAL 0x00000000 | |
48 | #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 | |
49 | #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ | |
50 | ||
51 | /* clocks */ | |
52 | #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ | |
53 | #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */ | |
54 | #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */ | |
55 | ||
56 | /* sdram */ | |
57 | #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */ | |
58 | #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 | |
59 | #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 | |
60 | #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ | |
61 | #define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */ | |
62 | #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ | |
63 | #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ | |
64 | #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ | |
65 | #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ | |
66 | #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ | |
67 | #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ | |
68 | #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ | |
69 | #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ | |
70 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ | |
71 | ||
dbbf13ba AB |
72 | #define CONFIG_ATMEL_USART |
73 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
74 | #define CONFIG_USART_ID 0/* ignored in arm */ | |
d8380c9d | 75 | |
af4b8b4b | 76 | #undef CONFIG_HARD_I2C |
af4b8b4b EB |
77 | #define AT91_PIN_SDA (1<<25) |
78 | #define AT91_PIN_SCL (1<<26) | |
79 | ||
632f8fdf | 80 | #define CONFIG_SYS_I2C_INIT_BOARD |
af4b8b4b EB |
81 | #define CONFIG_SYS_I2C_SPEED 50000 |
82 | #define CONFIG_SYS_I2C_SLAVE 0 | |
83 | ||
84 | #define I2C_INIT i2c_init_board(); | |
85 | #define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); | |
86 | #define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); | |
87 | #define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) | |
88 | #define I2C_SDA(bit) \ | |
89 | if (bit) \ | |
90 | writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ | |
91 | else \ | |
92 | writel(AT91_PMX_AA_TWD, &pio->pioa.codr); | |
93 | #define I2C_SCL(bit) \ | |
94 | if (bit) \ | |
95 | writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ | |
96 | else \ | |
97 | writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); | |
98 | ||
99 | #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) | |
d8380c9d | 100 | |
d8380c9d TR |
101 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
103 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 | |
104 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
d8380c9d | 105 | |
632f8fdf EB |
106 | #define CONFIG_BOOTP_BOOTFILESIZE |
107 | #define CONFIG_BOOTP_BOOTPATH | |
108 | #define CONFIG_BOOTP_GATEWAY | |
109 | #define CONFIG_BOOTP_HOSTNAME | |
d8380c9d | 110 | |
632f8fdf EB |
111 | #define CONFIG_CMD_PING |
112 | #define CONFIG_CMD_MII | |
113 | #define CONFIG_CMD_CACHE | |
d8380c9d | 114 | #undef CONFIG_CMD_USB |
632f8fdf | 115 | #undef CONFIG_CMD_DHCP |
d8380c9d | 116 | |
ea818dbb | 117 | #ifdef CONFIG_SYS_I2C_SOFT |
632f8fdf EB |
118 | #define CONFIG_CMD_EEPROM |
119 | #define CONFIG_CMD_I2C | |
120 | #endif | |
d8380c9d TR |
121 | |
122 | #define CONFIG_NR_DRAM_BANKS 1 | |
632f8fdf EB |
123 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
124 | #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) | |
d8380c9d | 125 | |
632f8fdf | 126 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
d8380c9d | 127 | #define CONFIG_SYS_MEMTEST_END \ |
632f8fdf | 128 | (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) |
d8380c9d | 129 | |
632f8fdf EB |
130 | #define CONFIG_DRIVER_AT91EMAC |
131 | #define CONFIG_SYS_RX_ETH_BUFFER 16 | |
132 | #define CONFIG_RMII | |
133 | #define CONFIG_MII | |
836cd453 | 134 | #define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 |
d8380c9d | 135 | #define CONFIG_NET_RETRY_COUNT 20 |
632f8fdf | 136 | #define CONFIG_KS8721_PHY |
d8380c9d | 137 | |
632f8fdf EB |
138 | #define CONFIG_SYS_FLASH_CFI |
139 | #define CONFIG_FLASH_CFI_DRIVER | |
140 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
141 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
d8380c9d | 142 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
632f8fdf | 143 | #define CONFIG_SYS_FLASH_PROTECTION |
d8380c9d TR |
144 | #define PHYS_FLASH_1 0x10000000 |
145 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
146 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
af4b8b4b | 147 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
632f8fdf EB |
148 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
149 | #define PHYS_FLASH_SIZE (16 * 1024 * 1024) | |
150 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
151 | { PHYS_FLASH_1 } | |
d8380c9d TR |
152 | |
153 | #if defined(CONFIG_CMD_USB) | |
632f8fdf | 154 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 155 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
632f8fdf EB |
156 | #define CONFIG_USB_OHCI_NEW |
157 | #define CONFIG_USB_STORAGE | |
158 | #define CONFIG_DOS_PARTITION | |
159 | #define CONFIG_AT91C_PQFP_UHPBU | |
d8380c9d | 160 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
632f8fdf | 161 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
d8380c9d TR |
162 | #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE |
163 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" | |
164 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
165 | #endif | |
166 | ||
632f8fdf EB |
167 | #define CONFIG_ENV_IS_IN_FLASH |
168 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024) | |
169 | #define CONFIG_ENV_SIZE (128 * 1024) | |
170 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
d8380c9d TR |
171 | |
172 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 | |
173 | ||
174 | #define CONFIG_BAUDRATE 115200 | |
d8380c9d | 175 | |
d8380c9d TR |
176 | #define CONFIG_SYS_CBSIZE 256 |
177 | #define CONFIG_SYS_MAXARGS 32 | |
178 | #define CONFIG_SYS_PBSIZE \ | |
179 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
632f8fdf | 180 | #define CONFIG_CMDLINE_EDITING |
d8380c9d | 181 | |
632f8fdf EB |
182 | #define CONFIG_SYS_MALLOC_LEN \ |
183 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024) | |
184 | ||
185 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ | |
186 | GENERATED_GBL_DATA_SIZE) | |
d8380c9d | 187 | |
632f8fdf EB |
188 | #define CONFIG_DEVICE_NULLDEV |
189 | #define CONFIG_SILENT_CONSOLE | |
d8380c9d | 190 | |
632f8fdf | 191 | #define CONFIG_VERSION_VARIABLE |
d8380c9d TR |
192 | |
193 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0" | |
194 | #define MTDPARTS_DEFAULT \ | |
195 | "mtdparts=physmap-flash.0:" \ | |
196 | "128k(u-boot)ro," \ | |
197 | "128k(u-boot-env)," \ | |
0ca6c526 | 198 | "1792k(kernel)," \ |
d8380c9d TR |
199 | "-(rootfs)" |
200 | ||
201 | #define CONFIG_BOOTARGS \ | |
202 | "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200" | |
203 | ||
204 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
205 | ||
206 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
207 | "mtdid=" MTDIDS_DEFAULT "\0" \ | |
208 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
209 | "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \ | |
210 | "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ | |
211 | "10000000 ${filesize}\0" \ | |
212 | "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ | |
0ca6c526 | 213 | "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \ |
d8380c9d TR |
214 | "10040000 ${filesize}\0" \ |
215 | "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ | |
0ca6c526 EB |
216 | "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \ |
217 | "21000000 10200000 ${filesize}\0" \ | |
d8380c9d TR |
218 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ |
219 | "flashboot=run ramargs;bootm 10040000\0" \ | |
220 | "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ | |
221 | "bootm 21000000\0" | |
af4b8b4b | 222 | #endif /* _CONFIG_CPUAT91_H */ |