[people/ms/u-boot.git] / include / configs / cpuat91.h

/*
 * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
 * eric@eukrea.com
 *
 * Configuration settings for the CPUAT91 board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _CONFIG_CPUAT91_H
#define _CONFIG_CPUAT91_H

#include <asm/sizes.h>

#ifdef CONFIG_RAMBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE		0x21F00000
#else
#define CONFIG_BOOTDELAY		1
#define CONFIG_SYS_TEXT_BASE		0
#endif

#define AT91C_XTAL_CLOCK		18432000
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
#define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
#define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3)
#define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
#define CONFIG_SYS_HZ			1000

#define CONFIG_ARM920T
#define CONFIG_AT91RM9200
#define CONFIG_CPUAT91
#define USE_920T_MMU

#include <asm/hardware.h>	/* needed for port definitions */

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOARD_EARLY_INIT_F

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR
/* flash */
#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
#define CONFIG_SYS_MC_PUP_VAL	0x00000000
#define CONFIG_SYS_MC_PUER_VAL	0x00000000
#define CONFIG_SYS_MC_ASR_VAL	0x00000000
#define CONFIG_SYS_MC_AASR_VAL	0x00000000
#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz for USB */
#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock */

/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as D16/D31 */
#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
#define CONFIG_SYS_SDRC_CR_VAL	0x2188C155 /* set up the SDRAM */
#define CONFIG_SYS_SDRAM	0x20000000 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the SDRAM */
#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to SDRAM */
#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */

#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
#define CONFIG_USART_ID		0/* ignored in arm */

#undef CONFIG_HARD_I2C
#define AT91_PIN_SDA			(1<<25)
#define AT91_PIN_SCL			(1<<26)

#define CONFIG_SYS_I2C_INIT_BOARD
#define	CONFIG_SYS_I2C_SPEED		50000
#define CONFIG_SYS_I2C_SLAVE		0

#define I2C_INIT	i2c_init_board();
#define I2C_ACTIVE	writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
#define I2C_TRISTATE	writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
#define I2C_READ	((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
#define I2C_SDA(bit)						\
	if (bit)						\
		writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);	\
	else							\
		writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
#define I2C_SCL(bit)						\
	if (bit)						\
		writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);	\
	else							\
		writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);

#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)

#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_DHCP

#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#endif

#define CONFIG_NR_DRAM_BANKS			1
#define CONFIG_SYS_SDRAM_BASE			0x20000000
#define CONFIG_SYS_SDRAM_SIZE			(32 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			\
	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)

#define CONFIG_DRIVER_AT91EMAC
#define CONFIG_SYS_RX_ETH_BUFFER	16
#define CONFIG_RMII
#define CONFIG_MII
#define CONFIG_DRIVER_AT91EMAC_PHYADDR	1
#define CONFIG_NET_RETRY_COUNT			20
#define CONFIG_KS8721_PHY

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_FLASH_PROTECTION
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		128
#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
#define PHYS_FLASH_SIZE				(16 * 1024 * 1024)
#define CONFIG_SYS_FLASH_BANKS_LIST		\
		{ PHYS_FLASH_1 }

#if defined(CONFIG_CMD_USB)
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_AT91C_PQFP_UHPBU
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#endif

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR				(PHYS_FLASH_1 + 128 * 1024)
#define CONFIG_ENV_SIZE				(128 * 1024)
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)

#define CONFIG_SYS_LOAD_ADDR		0x21000000

#define CONFIG_BAUDRATE			115200

#define CONFIG_SYS_PROMPT		"CPUAT91=> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		32
#define CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING

#define CONFIG_SYS_MALLOC_LEN		\
			ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
				GENERATED_GBL_DATA_SIZE)

#define CONFIG_DEVICE_NULLDEV
#define CONFIG_SILENT_CONSOLE

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"Press SPACE to abort autoboot\n"
#define CONFIG_AUTOBOOT_STOP_STR	" "
#define CONFIG_AUTOBOOT_DELAY_STR	"d"

#define CONFIG_VERSION_VARIABLE

#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT		\
	"mtdparts=physmap-flash.0:"	\
		"128k(u-boot)ro,"	\
		"128k(u-boot-env),"	\
		"1792k(kernel),"	\
		"-(rootfs)"

#define CONFIG_BOOTARGS 		\
	"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"

#define CONFIG_BOOTCOMMAND		"run flashboot"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"mtdid=" MTDIDS_DEFAULT "\0"					\
	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
	"flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 "	\
		"1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 "	\
		"10000000 ${filesize}\0"				\
	"flui=tftp 21000000 cpuat91/uImage; protect off 10040000 "	\
		"1019ffff; erase 10040000 101fffff; cp.b 21000000 "	\
		"10040000 ${filesize}\0"				\
	"flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off "	\
		"10200000 10ffffff; erase 10200000 10ffffff; cp.b "	\
		"21000000 10200000 ${filesize}\0"			\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"		\
	"flashboot=run ramargs;bootm 10040000\0"			\
	"netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;"		\
		"bootm 21000000\0"
#endif	/* _CONFIG_CPUAT91_H */
Commit	Line	Data
d8380c9d	1	/*
af4b8b4b	2	* CPUAT91 by (C) Copyright 2006-2010 Eric Benard
d8380c9d TR	3	* eric@eukrea.com
	4	*
	5	* Configuration settings for the CPUAT91 board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
af4b8b4b EB	26	#ifndef _CONFIG_CPUAT91_H
af4b8b4b EB	27	#define _CONFIG_CPUAT91_H
425de62d	28
632f8fdf EB	29	#include <asm/sizes.h>
	30
	31	#ifdef CONFIG_RAMBOOT
	32	#define CONFIG_SKIP_LOWLEVEL_INIT
	33	#define CONFIG_SYS_TEXT_BASE 0x21F00000
d8380c9d TR	34	#else
d8380c9d TR	35	#define CONFIG_BOOTDELAY 1
632f8fdf	36	#define CONFIG_SYS_TEXT_BASE 0
d8380c9d TR	37	#endif
d8380c9d TR	38
632f8fdf	39	#define AT91C_XTAL_CLOCK 18432000
6a372e94	40	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
632f8fdf EB	41	#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
	42	#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
	43	#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
	44	#define CONFIG_SYS_HZ 1000
d8380c9d	45
632f8fdf EB	46	#define CONFIG_ARM920T
	47	#define CONFIG_AT91RM9200
	48	#define CONFIG_CPUAT91
632f8fdf	49	#define USE_920T_MMU
d8380c9d	50
6a372e94 AB	51	#include <asm/hardware.h> /* needed for port definitions */
6a372e94 AB	52
632f8fdf EB	53	#define CONFIG_CMDLINE_TAG
	54	#define CONFIG_SETUP_MEMORY_TAGS
	55	#define CONFIG_INITRD_TAG
dbbf13ba	56	#define CONFIG_BOARD_EARLY_INIT_F
d8380c9d TR	57
d8380c9d TR	58	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
632f8fdf	59	#define CONFIG_SYS_USE_MAIN_OSCILLATOR
d8380c9d TR	60	/* flash */
	61	#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
	62	#define CONFIG_SYS_MC_PUP_VAL 0x00000000
	63	#define CONFIG_SYS_MC_PUER_VAL 0x00000000
	64	#define CONFIG_SYS_MC_ASR_VAL 0x00000000
	65	#define CONFIG_SYS_MC_AASR_VAL 0x00000000
	66	#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
	67	#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	68
	69	/* clocks */
	70	#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
	71	#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
	72	#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
	73
	74	/* sdram */
	75	#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
	76	#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
	77	#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
	78	#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	79	#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
	80	#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
	81	#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
	82	#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
	83	#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
	84	#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
	85	#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	86	#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	87	#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
	88	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
	89
dbbf13ba AB	90	#define CONFIG_ATMEL_USART
	91	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	92	#define CONFIG_USART_ID 0/* ignored in arm */
d8380c9d	93
af4b8b4b	94	#undef CONFIG_HARD_I2C
af4b8b4b EB	95	#define AT91_PIN_SDA (1<<25)
	96	#define AT91_PIN_SCL (1<<26)
	97
632f8fdf	98	#define CONFIG_SYS_I2C_INIT_BOARD
af4b8b4b EB	99	#define CONFIG_SYS_I2C_SPEED 50000
	100	#define CONFIG_SYS_I2C_SLAVE 0
	101
	102	#define I2C_INIT i2c_init_board();
	103	#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
	104	#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
	105	#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
	106	#define I2C_SDA(bit) \
	107	if (bit) \
	108	writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
	109	else \
	110	writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
	111	#define I2C_SCL(bit) \
	112	if (bit) \
	113	writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
	114	else \
	115	writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
	116
	117	#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
d8380c9d	118
d8380c9d TR	119	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	120	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	121	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
	122	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
d8380c9d	123
632f8fdf EB	124	#define CONFIG_BOOTP_BOOTFILESIZE
	125	#define CONFIG_BOOTP_BOOTPATH
	126	#define CONFIG_BOOTP_GATEWAY
	127	#define CONFIG_BOOTP_HOSTNAME
d8380c9d TR	128
	129	#include <config_cmd_default.h>
	130
632f8fdf EB	131	#define CONFIG_CMD_PING
	132	#define CONFIG_CMD_MII
	133	#define CONFIG_CMD_CACHE
d8380c9d TR	134	#undef CONFIG_CMD_USB
	135	#undef CONFIG_CMD_FPGA
	136	#undef CONFIG_CMD_IMI
	137	#undef CONFIG_CMD_LOADS
	138	#undef CONFIG_CMD_NFS
632f8fdf	139	#undef CONFIG_CMD_DHCP
d8380c9d	140
ea818dbb	141	#ifdef CONFIG_SYS_I2C_SOFT
632f8fdf EB	142	#define CONFIG_CMD_EEPROM
	143	#define CONFIG_CMD_I2C
	144	#endif
d8380c9d TR	145
d8380c9d TR	146	#define CONFIG_NR_DRAM_BANKS 1
632f8fdf EB	147	#define CONFIG_SYS_SDRAM_BASE 0x20000000
632f8fdf EB	148	#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
d8380c9d	149
632f8fdf	150	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
d8380c9d	151	#define CONFIG_SYS_MEMTEST_END \
632f8fdf	152	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
d8380c9d	153
632f8fdf EB	154	#define CONFIG_DRIVER_AT91EMAC
	155	#define CONFIG_SYS_RX_ETH_BUFFER 16
	156	#define CONFIG_RMII
	157	#define CONFIG_MII
836cd453	158	#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
d8380c9d	159	#define CONFIG_NET_RETRY_COUNT 20
632f8fdf	160	#define CONFIG_KS8721_PHY
d8380c9d	161
632f8fdf EB	162	#define CONFIG_SYS_FLASH_CFI
	163	#define CONFIG_FLASH_CFI_DRIVER
	164	#define CONFIG_SYS_FLASH_EMPTY_INFO
	165	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
d8380c9d	166	#define CONFIG_SYS_MAX_FLASH_BANKS 1
632f8fdf	167	#define CONFIG_SYS_FLASH_PROTECTION
d8380c9d TR	168	#define PHYS_FLASH_1 0x10000000
	169	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	170	#define CONFIG_SYS_MAX_FLASH_SECT 128
af4b8b4b	171	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
632f8fdf EB	172	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	173	#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
	174	#define CONFIG_SYS_FLASH_BANKS_LIST \
	175	{ PHYS_FLASH_1 }
d8380c9d TR	176
d8380c9d TR	177	#if defined(CONFIG_CMD_USB)
632f8fdf EB	178	#define CONFIG_USB_ATMEL
	179	#define CONFIG_USB_OHCI_NEW
	180	#define CONFIG_USB_STORAGE
	181	#define CONFIG_DOS_PARTITION
	182	#define CONFIG_AT91C_PQFP_UHPBU
d8380c9d	183	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
632f8fdf	184	#define CONFIG_SYS_USB_OHCI_CPU_INIT
d8380c9d TR	185	#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
	186	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
	187	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	188	#endif
	189
632f8fdf EB	190	#define CONFIG_ENV_IS_IN_FLASH
	191	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
	192	#define CONFIG_ENV_SIZE (128 * 1024)
	193	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
d8380c9d TR	194
	195	#define CONFIG_SYS_LOAD_ADDR 0x21000000
	196
	197	#define CONFIG_BAUDRATE 115200
d8380c9d TR	198
	199	#define CONFIG_SYS_PROMPT "CPUAT91=> "
	200	#define CONFIG_SYS_CBSIZE 256
	201	#define CONFIG_SYS_MAXARGS 32
	202	#define CONFIG_SYS_PBSIZE \
	203	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
632f8fdf	204	#define CONFIG_CMDLINE_EDITING
d8380c9d	205
632f8fdf EB	206	#define CONFIG_SYS_MALLOC_LEN \
	207	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
	208
	209	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
	210	GENERATED_GBL_DATA_SIZE)
d8380c9d	211
632f8fdf EB	212	#define CONFIG_DEVICE_NULLDEV
632f8fdf EB	213	#define CONFIG_SILENT_CONSOLE
d8380c9d	214
632f8fdf	215	#define CONFIG_AUTOBOOT_KEYED
513bbe1b EB	216	#define CONFIG_AUTOBOOT_PROMPT \
513bbe1b EB	217	"Press SPACE to abort autoboot\n"
d8380c9d TR	218	#define CONFIG_AUTOBOOT_STOP_STR " "
	219	#define CONFIG_AUTOBOOT_DELAY_STR "d"
	220
632f8fdf	221	#define CONFIG_VERSION_VARIABLE
d8380c9d TR	222
	223	#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
	224	#define MTDPARTS_DEFAULT \
	225	"mtdparts=physmap-flash.0:" \
	226	"128k(u-boot)ro," \
	227	"128k(u-boot-env)," \
0ca6c526	228	"1792k(kernel)," \
d8380c9d TR	229	"-(rootfs)"
	230
	231	#define CONFIG_BOOTARGS \
	232	"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
	233
	234	#define CONFIG_BOOTCOMMAND "run flashboot"
	235
	236	#define CONFIG_EXTRA_ENV_SETTINGS \
	237	"mtdid=" MTDIDS_DEFAULT "\0" \
	238	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	239	"flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
	240	"1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
	241	"10000000 ${filesize}\0" \
	242	"flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
0ca6c526	243	"1019ffff; erase 10040000 101fffff; cp.b 21000000 " \
d8380c9d TR	244	"10040000 ${filesize}\0" \
d8380c9d TR	245	"flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
0ca6c526 EB	246	"10200000 10ffffff; erase 10200000 10ffffff; cp.b " \
0ca6c526 EB	247	"21000000 10200000 ${filesize}\0" \
d8380c9d TR	248	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	249	"flashboot=run ramargs;bootm 10040000\0" \
	250	"netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
	251	"bootm 21000000\0"
af4b8b4b	252	#endif /* _CONFIG_CPUAT91_H */