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d9fd6ff5 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
d9fd6ff5 WD |
31 | /* |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
36 | #define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ | |
37 | ||
38 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
39 | ||
b3acb6cd JCPV |
40 | /* we will never enable dcache, because we have to setup MMU first */ |
41 | #define CONFIG_SYS_NO_DCACHE | |
eb0e11bd | 42 | #define CONFIG_SYS_TEXT_BASE 0x0 |
d9fd6ff5 WD |
43 | /* |
44 | * Size of malloc() pool | |
45 | */ | |
6d0f6bcf | 46 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
d9fd6ff5 WD |
47 | |
48 | /* | |
49 | * Hardware drivers | |
50 | */ | |
7194ab80 BW |
51 | #define CONFIG_NET_MULTI |
52 | #define CONFIG_SMC91111 | |
d9fd6ff5 WD |
53 | #define CONFIG_SMC91111_BASE 0x10000300 |
54 | #define CONFIG_SMC91111_EXT_PHY | |
55 | #define CONFIG_SMC_USE_32_BIT | |
56 | ||
57 | /* | |
58 | * select serial console configuration | |
59 | */ | |
379be585 | 60 | #define CONFIG_PXA_SERIAL |
d9fd6ff5 WD |
61 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ |
62 | ||
63 | /* allow to overwrite serial and ethaddr */ | |
64 | #define CONFIG_ENV_OVERWRITE | |
65 | ||
66 | #define CONFIG_BAUDRATE 115200 | |
67 | ||
d9fd6ff5 | 68 | |
80ff4f99 JL |
69 | /* |
70 | * BOOTP options | |
71 | */ | |
72 | #define CONFIG_BOOTP_BOOTFILESIZE | |
73 | #define CONFIG_BOOTP_BOOTPATH | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | ||
77 | ||
37e4f24b JL |
78 | /* |
79 | * Command line configuration. | |
80 | */ | |
81 | #include <config_cmd_default.h> | |
82 | ||
d9fd6ff5 WD |
83 | |
84 | #define CONFIG_BOOTDELAY 3 | |
85 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" | |
86 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
87 | #define CONFIG_NETMASK 255.255.0.0 | |
88 | #define CONFIG_IPADDR 192.168.0.21 | |
89 | #define CONFIG_SERVERIP 192.168.0.250 | |
90 | #define CONFIG_BOOTCOMMAND "bootm 40000" | |
91 | #define CONFIG_CMDLINE_TAG | |
92 | ||
93 | /* | |
94 | * Miscellaneous configurable options | |
95 | */ | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
97 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
99 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
100 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
101 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d9fd6ff5 | 102 | |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
104 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
d9fd6ff5 | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ |
d9fd6ff5 | 107 | |
94a33129 | 108 | #define CONFIG_SYS_HZ 1000 |
6d0f6bcf | 109 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
d9fd6ff5 | 110 | |
8bde7f77 | 111 | /* valid baudrates */ |
6d0f6bcf | 112 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
d9fd6ff5 WD |
113 | |
114 | /* | |
115 | * Stack sizes | |
116 | * | |
117 | * The stack sizes are set up in start.S using the settings below | |
118 | */ | |
119 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
120 | #ifdef CONFIG_USE_IRQ | |
121 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
122 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
123 | #endif | |
124 | ||
125 | /* | |
126 | * Physical Memory Map | |
127 | */ | |
eb0e11bd | 128 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
d9fd6ff5 WD |
129 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
130 | #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ | |
d9fd6ff5 WD |
131 | |
132 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
133 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ | |
134 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
135 | ||
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
137 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
d9fd6ff5 | 138 | |
6d0f6bcf | 139 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
d9fd6ff5 | 140 | |
6ef6eb91 | 141 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
25ddd1fb | 142 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
6ef6eb91 | 143 | |
d9fd6ff5 WD |
144 | /* |
145 | * FLASH and environment organization | |
146 | */ | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
148 | #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ | |
d9fd6ff5 WD |
149 | |
150 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
152 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
d9fd6ff5 | 153 | |
5a1aceb0 | 154 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
155 | #define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */ |
156 | #define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ | |
d9fd6ff5 WD |
157 | |
158 | /****************************************************************************** | |
159 | * | |
160 | * CPU specific defines | |
161 | * | |
162 | ******************************************************************************/ | |
163 | ||
164 | /* | |
165 | * GPIO settings | |
166 | * | |
167 | * GPIO pin assignments | |
168 | * GPIO Name Dir Out AF | |
169 | * 0 NC | |
170 | * 1 NC | |
171 | * 2 SIRQ1 I | |
172 | * 3 SIRQ2 I | |
173 | * 4 SIRQ3 I | |
174 | * 5 DMAACK1 O 0 | |
175 | * 6 DMAACK2 O 0 | |
176 | * 7 DMAACK3 O 0 | |
177 | * 8 TC1 O 0 | |
178 | * 9 TC2 O 0 | |
179 | * 10 TC3 O 0 | |
180 | * 11 nDMAEN O 1 | |
181 | * 12 AENCTRL O 0 | |
182 | * 13 PLDTC O 0 | |
183 | * 14 ETHIRQ I | |
184 | * 15 NC | |
185 | * 16 NC | |
186 | * 17 NC | |
187 | * 18 RDY I | |
188 | * 19 DMASIO I | |
189 | * 20 ETHIRQ NC | |
190 | * 21 NC | |
191 | * 22 PGMEN O 1 FIXME for debug only enable flash | |
192 | * 23 NC | |
193 | * 24 NC | |
194 | * 25 NC | |
195 | * 26 NC | |
196 | * 27 NC | |
197 | * 28 NC | |
198 | * 29 NC | |
199 | * 30 NC | |
200 | * 31 NC | |
201 | * 32 NC | |
202 | * 33 NC | |
203 | * 34 FFRXD I 01 | |
204 | * 35 FFCTS I 01 | |
205 | * 36 FFDCD I 01 | |
206 | * 37 FFDSR I 01 | |
207 | * 38 FFRI I 01 | |
208 | * 39 FFTXD O 1 10 | |
209 | * 40 FFDTR O 0 10 | |
210 | * 41 FFRTS O 0 10 | |
211 | * 42 RS232FOFF O 0 00 | |
212 | * 43 NC | |
213 | * 44 NC | |
214 | * 45 IRSL0 O 0 | |
215 | * 46 IRRX0 I 01 | |
216 | * 47 IRTX0 O 0 10 | |
217 | * 48 NC | |
218 | * 49 nIOWE O 0 | |
219 | * 50 NC | |
220 | * 51 NC | |
221 | * 52 NC | |
222 | * 53 NC | |
223 | * 54 NC | |
224 | * 55 NC | |
225 | * 56 NC | |
226 | * 57 NC | |
227 | * 58 DKDIRQ I | |
228 | * 59 NC | |
229 | * 60 NC | |
230 | * 61 NC | |
231 | * 62 NC | |
232 | * 63 NC | |
233 | * 64 COMLED O 0 | |
234 | * 65 COMLED O 0 | |
235 | * 66 COMLED O 0 | |
236 | * 67 COMLED O 0 | |
237 | * 68 COMLED O 0 | |
238 | * 69 COMLED O 0 | |
239 | * 70 COMLED O 0 | |
240 | * 71 COMLED O 0 | |
241 | * 72 NC | |
242 | * 73 NC | |
243 | * 74 NC | |
244 | * 75 NC | |
245 | * 76 NC | |
246 | * 77 NC | |
247 | * 78 CSIO O 1 | |
248 | * 79 NC | |
249 | * 80 CSETH O 1 | |
250 | * | |
251 | * NOTE: All NC's are defined to be outputs | |
252 | * | |
253 | */ | |
254 | /* Pin direction control */ | |
255 | /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_GPDR0_VAL 0xfff3bf02 |
257 | #define CONFIG_SYS_GPDR1_VAL 0xfbffbf83 | |
258 | #define CONFIG_SYS_GPDR2_VAL 0x0001ffff | |
d9fd6ff5 | 259 | /* Set and Clear registers */ |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_GPSR0_VAL 0x00400800 |
261 | #define CONFIG_SYS_GPSR1_VAL 0x00000480 | |
262 | #define CONFIG_SYS_GPSR2_VAL 0x00014000 | |
263 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | |
264 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
265 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
d9fd6ff5 | 266 | /* Edge detect registers (these are set by the kernel) */ |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_GRER0_VAL 0x00000000 |
268 | #define CONFIG_SYS_GRER1_VAL 0x00000000 | |
269 | #define CONFIG_SYS_GRER2_VAL 0x00000000 | |
270 | #define CONFIG_SYS_GFER0_VAL 0x00000000 | |
271 | #define CONFIG_SYS_GFER1_VAL 0x00000000 | |
272 | #define CONFIG_SYS_GFER2_VAL 0x00000000 | |
d9fd6ff5 | 273 | /* Alternate function registers */ |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_GAFR0_L_VAL 0x00000000 |
275 | #define CONFIG_SYS_GAFR0_U_VAL 0x00000010 | |
276 | #define CONFIG_SYS_GAFR1_L_VAL 0x900a9550 | |
277 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 | |
278 | #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 | |
279 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | |
d9fd6ff5 WD |
280 | |
281 | /* | |
282 | * Clocks, power control and interrupts | |
283 | */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_PSSR_VAL 0x00000020 |
eb0e11bd MV |
285 | #define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */ |
286 | #define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */ | |
287 | #define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */ | |
d9fd6ff5 WD |
288 | |
289 | /* FIXME | |
290 | * | |
291 | * RTC settings | |
292 | * Watchdog | |
293 | * | |
294 | */ | |
295 | ||
296 | /* | |
297 | * Memory settings | |
298 | * | |
299 | * FIXME Can ethernet be burst read and/or write?? This is set for lubbock | |
300 | * Verify timings on all | |
301 | */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */ |
303 | /*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ | |
304 | #define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ | |
305 | #define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ | |
d9fd6ff5 | 306 | #ifdef REDBOOT_WAY |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ |
308 | #define CONFIG_SYS_MDMRS_VAL 0x00000000 | |
309 | #define CONFIG_SYS_MDREFR_VAL 0x00018018 | |
d9fd6ff5 | 310 | #else |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ |
312 | #define CONFIG_SYS_MDMRS_VAL 0x00000000 | |
313 | #define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ | |
d9fd6ff5 | 314 | #endif |
eb0e11bd MV |
315 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
316 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | |
d9fd6ff5 WD |
317 | |
318 | /* | |
319 | * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) | |
320 | */ | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
322 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 | |
323 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 | |
324 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 | |
325 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 | |
326 | #define CONFIG_SYS_MCIO0_VAL 0x00004715 | |
327 | #define CONFIG_SYS_MCIO1_VAL 0x00004715 | |
d9fd6ff5 WD |
328 | |
329 | /* Board specific defines */ | |
330 | ||
331 | /* LED defines */ | |
332 | #define YELLOW 0x03 | |
333 | #define RED 0x02 | |
334 | #define GREEN 0x01 | |
335 | #define OFF 0x00 | |
336 | #define LED_IRDA0 0 | |
337 | #define LED_IRDA1 2 | |
338 | #define LED_IRDA2 4 | |
339 | #define LED_IRDA3 6 | |
d9fd6ff5 WD |
340 | |
341 | /* SuperIO defines */ | |
342 | #define CRADLE_SIO_INDEX 0x2e | |
343 | #define CRADLE_SIO_DATA 0x2f | |
344 | ||
345 | /* IO defines */ | |
346 | #define CRADLE_CPLD_PHYS 0x08000000 | |
347 | #define CRADLE_SIO1_PHYS 0x08100000 | |
348 | #define CRADLE_SIO2_PHYS 0x08200000 | |
349 | #define CRADLE_SIO3_PHYS 0x08300000 | |
350 | #define CRADLE_ETH_PHYS 0x10000000 | |
351 | ||
352 | #ifndef __ASSEMBLY__ | |
353 | ||
354 | /* global prototypes */ | |
355 | void led_code(int code, int color); | |
356 | ||
357 | #endif | |
358 | ||
359 | #endif /* __CONFIG_H */ |