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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. | |
4 | * | |
5 | * Configuration for the Cogent CSB226 board. For details see | |
6 | * http://www.cogcomp.com/csb_csb226.htm | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * include/configs/csb226.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
699b13a6 WD |
34 | #define DEBUG 1 |
35 | ||
fe8c2806 WD |
36 | /* |
37 | * High Level Configuration Options | |
38 | * (easy to change) | |
39 | */ | |
53677ef1 | 40 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
fe8c2806 WD |
41 | #define CONFIG_CSB226 1 /* on a CSB226 board */ |
42 | ||
43 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
44 | /* for timer/console/ethernet */ | |
b3acb6cd JCPV |
45 | |
46 | /* we will never enable dcache, because we have to setup MMU first */ | |
47 | #define CONFIG_SYS_NO_DCACHE | |
48 | ||
fe8c2806 WD |
49 | /* |
50 | * Hardware drivers | |
51 | */ | |
52 | ||
53 | /* | |
54 | * select serial console configuration | |
55 | */ | |
379be585 | 56 | #define CONFIG_PXA_SERIAL |
47cd00fa | 57 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ |
fe8c2806 WD |
58 | |
59 | /* allow to overwrite serial and ethaddr */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
61 | ||
62 | #define CONFIG_BAUDRATE 19200 | |
47cd00fa | 63 | #undef CONFIG_MISC_INIT_R /* not used yet */ |
fe8c2806 | 64 | |
fe8c2806 | 65 | |
80ff4f99 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_BOOTFILESIZE | |
70 | #define CONFIG_BOOTP_BOOTPATH | |
71 | #define CONFIG_BOOTP_GATEWAY | |
72 | #define CONFIG_BOOTP_HOSTNAME | |
73 | ||
74 | ||
37e4f24b JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
80 | #define CONFIG_CMD_BDI | |
81 | #define CONFIG_CMD_LOADB | |
82 | #define CONFIG_CMD_IMI | |
83 | #define CONFIG_CMD_FLASH | |
84 | #define CONFIG_CMD_MEMORY | |
85 | #define CONFIG_CMD_NET | |
bdab39d3 | 86 | #define CONFIG_CMD_SAVEENV |
37e4f24b JL |
87 | #define CONFIG_CMD_RUN |
88 | #define CONFIG_CMD_ASKENV | |
89 | #define CONFIG_CMD_ECHO | |
90 | #define CONFIG_CMD_DHCP | |
91 | #define CONFIG_CMD_CACHE | |
92 | ||
fe8c2806 | 93 | |
699b13a6 | 94 | #define CONFIG_BOOTDELAY 3 |
993cad93 | 95 | #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" |
fe8c2806 WD |
96 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF |
97 | #define CONFIG_NETMASK 255.255.255.0 | |
98 | #define CONFIG_IPADDR 192.168.1.56 | |
993cad93 | 99 | #define CONFIG_SERVERIP 192.168.1.5 |
699b13a6 | 100 | #define CONFIG_BOOTCOMMAND "bootm 0x40000" |
384ae025 | 101 | #define CONFIG_SHOW_BOOT_PROGRESS |
fe8c2806 | 102 | |
47cd00fa WD |
103 | #define CONFIG_CMDLINE_TAG 1 |
104 | ||
37e4f24b | 105 | #if defined(CONFIG_CMD_KGDB) |
47cd00fa | 106 | #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ |
fe8c2806 WD |
107 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
108 | #endif | |
109 | ||
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
113 | ||
114 | /* | |
115 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
116 | * used for the RAM copy of the uboot code | |
117 | * | |
118 | */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_MALLOC_LEN (128*1024) |
120 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
fe8c2806 | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
123 | #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ | |
124 | #define CONFIG_SYS_CBSIZE 128 /* Console I/O Buffer Size */ | |
125 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
126 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
127 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
fe8c2806 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
130 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
fe8c2806 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ |
fe8c2806 WD |
133 | /* RS: where is this documented? */ |
134 | /* RS: is this where U-Boot is */ | |
135 | /* RS: relocated to in RAM? */ | |
136 | ||
94a33129 | 137 | #define CONFIG_SYS_HZ 1000 |
fe8c2806 | 138 | /* RS: the oscillator is actually 3680130?? */ |
6d0f6bcf | 139 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
fe8c2806 WD |
140 | /* 0101000001 */ |
141 | /* ^^^^^ Memory Speed 99.53 MHz */ | |
142 | /* ^^ Run Mode Speed = 2x Mem Speed */ | |
143 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ | |
144 | ||
6d0f6bcf | 145 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ |
fe8c2806 | 146 | |
8bde7f77 | 147 | /* valid baudrates */ |
6d0f6bcf | 148 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
fe8c2806 | 149 | |
993cad93 WD |
150 | /* |
151 | * Network chip | |
152 | */ | |
b1c0eaac BW |
153 | #define CONFIG_NET_MULTI |
154 | #define CONFIG_CS8900 | |
155 | #define CONFIG_CS8900_BUS32 | |
156 | #define CONFIG_CS8900_BASE 0x08000000 | |
993cad93 | 157 | |
fe8c2806 WD |
158 | /* |
159 | * Stack sizes | |
160 | * | |
161 | * The stack sizes are set up in start.S using the settings below | |
162 | */ | |
163 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
164 | #ifdef CONFIG_USE_IRQ | |
165 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
166 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
167 | #endif | |
168 | ||
169 | /* | |
170 | * Physical Memory Map | |
171 | */ | |
172 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
173 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
174 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
175 | ||
176 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
177 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
178 | ||
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ |
180 | #define CONFIG_SYS_DRAM_SIZE 0x02000000 | |
fe8c2806 | 181 | |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
fe8c2806 | 183 | |
993cad93 WD |
184 | # if 0 |
185 | /* FIXME: switch to _documented_ registers */ | |
fe8c2806 WD |
186 | /* |
187 | * GPIO settings | |
993cad93 WD |
188 | * |
189 | * GP15 == nCS1 is 1 | |
190 | * GP24 == SFRM is 1 | |
191 | * GP25 == TXD is 1 | |
192 | * GP33 == nCS5 is 1 | |
193 | * GP39 == FFTXD is 1 | |
194 | * GP41 == RTS is 1 | |
195 | * GP47 == TXD is 1 | |
196 | * GP49 == nPWE is 1 | |
197 | * GP62 == LED_B is 1 | |
198 | * GP63 == TDM_OE is 1 | |
199 | * GP78 == nCS2 is 1 | |
200 | * GP79 == nCS3 is 1 | |
201 | * GP80 == nCS4 is 1 | |
202 | */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_GPSR0_VAL 0x03008000 |
204 | #define CONFIG_SYS_GPSR1_VAL 0xC0028282 | |
205 | #define CONFIG_SYS_GPSR2_VAL 0x0001C000 | |
993cad93 WD |
206 | |
207 | /* GP02 == DON_RST is 0 | |
208 | * GP23 == SCLK is 0 | |
209 | * GP45 == USB_ACT is 0 | |
210 | * GP60 == PLLEN is 0 | |
211 | * GP61 == LED_A is 0 | |
212 | * GP73 == SWUPD_LED is 0 | |
213 | */ | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_GPCR0_VAL 0x00800004 |
215 | #define CONFIG_SYS_GPCR1_VAL 0x30002000 | |
216 | #define CONFIG_SYS_GPCR2_VAL 0x00000100 | |
993cad93 WD |
217 | |
218 | /* GP00 == DON_READY is input | |
219 | * GP01 == DON_OK is input | |
220 | * GP02 == DON_RST is output | |
221 | * GP03 == RESET_IND is input | |
222 | * GP07 == RES11 is input | |
223 | * GP09 == RES12 is input | |
224 | * GP11 == SWUPDATE is input | |
225 | * GP14 == nPOWEROK is input | |
226 | * GP15 == nCS1 is output | |
227 | * GP17 == RES22 is input | |
228 | * GP18 == RDY is input | |
229 | * GP23 == SCLK is output | |
230 | * GP24 == SFRM is output | |
231 | * GP25 == TXD is output | |
232 | * GP26 == RXD is input | |
233 | * GP32 == RES21 is input | |
234 | * GP33 == nCS5 is output | |
235 | * GP34 == FFRXD is input | |
236 | * GP35 == CTS is input | |
237 | * GP39 == FFTXD is output | |
238 | * GP41 == RTS is output | |
239 | * GP42 == USB_OK is input | |
240 | * GP45 == USB_ACT is output | |
241 | * GP46 == RXD is input | |
242 | * GP47 == TXD is output | |
243 | * GP49 == nPWE is output | |
244 | * GP58 == nCPUBUSINT is input | |
245 | * GP59 == LANINT is input | |
246 | * GP60 == PLLEN is output | |
247 | * GP61 == LED_A is output | |
248 | * GP62 == LED_B is output | |
249 | * GP63 == TDM_OE is output | |
250 | * GP64 == nDSPINT is input | |
251 | * GP65 == STRAP0 is input | |
252 | * GP67 == STRAP1 is input | |
253 | * GP69 == STRAP2 is input | |
254 | * GP70 == STRAP3 is input | |
255 | * GP71 == STRAP4 is input | |
256 | * GP73 == SWUPD_LED is output | |
257 | * GP78 == nCS2 is output | |
258 | * GP79 == nCS3 is output | |
259 | * GP80 == nCS4 is output | |
260 | */ | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_GPDR0_VAL 0x03808004 |
262 | #define CONFIG_SYS_GPDR1_VAL 0xF002A282 | |
263 | #define CONFIG_SYS_GPDR2_VAL 0x0001C200 | |
993cad93 WD |
264 | |
265 | /* GP15 == nCS1 is AF10 | |
266 | * GP18 == RDY is AF01 | |
267 | * GP23 == SCLK is AF10 | |
268 | * GP24 == SFRM is AF10 | |
269 | * GP25 == TXD is AF10 | |
270 | * GP26 == RXD is AF01 | |
271 | * GP33 == nCS5 is AF10 | |
272 | * GP34 == FFRXD is AF01 | |
273 | * GP35 == CTS is AF01 | |
274 | * GP39 == FFTXD is AF10 | |
275 | * GP41 == RTS is AF10 | |
276 | * GP46 == RXD is AF10 | |
277 | * GP47 == TXD is AF01 | |
278 | * GP49 == nPWE is AF10 | |
279 | * GP78 == nCS2 is AF10 | |
280 | * GP79 == nCS3 is AF10 | |
281 | * GP80 == nCS4 is AF10 | |
fe8c2806 | 282 | */ |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 |
284 | #define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 | |
285 | #define CONFIG_SYS_GAFR1_L_VAL 0x60088058 | |
286 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 | |
287 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 | |
288 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | |
fe8c2806 | 289 | |
993cad93 WD |
290 | |
291 | /* FIXME: set GPIO_RER/FER */ | |
292 | ||
293 | /* RDH = 1 | |
294 | * PH = 1 | |
295 | * VFS = 1 | |
296 | * BFS = 1 | |
297 | * SSS = 1 | |
298 | */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_PSSR_VAL 0x37 |
993cad93 WD |
300 | |
301 | /* | |
302 | * Memory settings | |
303 | * | |
304 | * This is the configuration for nCS0/1 -> flash banks | |
305 | * configuration for nCS1: | |
306 | * [31] 0 - Slower Device | |
307 | * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
308 | * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
309 | * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
310 | * [19] 1 - 16 Bit bus width | |
311 | * [18:16] 000 - nonburst RAM or FLASH | |
312 | * configuration for nCS0: | |
313 | * [15] 0 - Slower Device | |
314 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
315 | * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
316 | * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
317 | * [03] 1 - 16 Bit bus width | |
318 | * [02:00] 000 - nonburst RAM or FLASH | |
319 | */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ |
993cad93 WD |
321 | |
322 | /* This is the configuration for nCS2/3 -> TDM-Switch, DSP | |
323 | * configuration for nCS3: DSP | |
324 | * [31] 0 - Slower Device | |
325 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
326 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
327 | * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns | |
328 | * [19] 1 - 16 Bit bus width | |
329 | * [18:16] 100 - variable latency I/O | |
330 | * configuration for nCS2: TDM-Switch | |
331 | * [15] 0 - Slower Device | |
332 | * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns | |
333 | * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns | |
334 | * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns | |
335 | * [03] 1 - 16 Bit bus width | |
336 | * [02:00] 100 - variable latency I/O | |
337 | */ | |
6d0f6bcf | 338 | #define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ |
993cad93 WD |
339 | |
340 | /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller | |
341 | * | |
342 | * configuration for nCS5: LAN Controller | |
343 | * [31] 0 - Slower Device | |
344 | * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
345 | * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
346 | * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns | |
347 | * [19] 1 - 16 Bit bus width | |
348 | * [18:16] 100 - variable latency I/O | |
349 | * configuration for nCS4: ExtBus | |
350 | * [15] 0 - Slower Device | |
351 | * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns | |
352 | * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns | |
353 | * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns | |
354 | * [03] 1 - 16 Bit bus width | |
355 | * [02:00] 100 - variable latency I/O | |
356 | */ | |
6d0f6bcf | 357 | #define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ |
993cad93 WD |
358 | |
359 | /* MDCNFG: SDRAM Configuration Register | |
360 | * | |
361 | * [31:29] 000 - reserved | |
362 | * [28] 0 - no SA1111 compatiblity mode | |
363 | * [27] 0 - latch return data with return clock | |
364 | * [26] 0 - alternate addressing for pair 2/3 | |
365 | * [25:24] 00 - timings | |
366 | * [23] 0 - internal banks in lower partition 2/3 (not used) | |
367 | * [22:21] 00 - row address bits for partition 2/3 (not used) | |
368 | * [20:19] 00 - column address bits for partition 2/3 (not used) | |
369 | * [18] 0 - SDRAM partition 2/3 width is 32 bit | |
370 | * [17] 0 - SDRAM partition 3 disabled | |
371 | * [16] 0 - SDRAM partition 2 disabled | |
372 | * [15:13] 000 - reserved | |
373 | * [12] 1 - SA1111 compatiblity mode | |
374 | * [11] 1 - latch return data with return clock | |
375 | * [10] 0 - no alternate addressing for pair 0/1 | |
376 | * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk | |
377 | * [7] 1 - 4 internal banks in lower partition pair | |
378 | * [06:05] 10 - 13 row address bits for partition 0/1 | |
379 | * [04:03] 01 - 9 column address bits for partition 0/1 | |
380 | * [02] 0 - SDRAM partition 0/1 width is 32 bit | |
381 | * [01] 0 - disable SDRAM partition 1 | |
382 | * [00] 1 - enable SDRAM partition 0 | |
383 | */ | |
384 | /* use the configuration above but disable partition 0 */ | |
6d0f6bcf | 385 | #define CONFIG_SYS_MDCNFG_VAL 0x000019c8 |
993cad93 WD |
386 | |
387 | /* MDREFR: SDRAM Refresh Control Register | |
388 | * | |
389 | * [32:26] 0 - reserved | |
390 | * [25] 0 - K2FREE: not free running | |
391 | * [24] 0 - K1FREE: not free running | |
392 | * [23] 1 - K0FREE: not free running | |
393 | * [22] 0 - SLFRSH: self refresh disabled | |
394 | * [21] 0 - reserved | |
395 | * [20] 0 - APD: no auto power down | |
396 | * [19] 0 - K2DB2: SDCLK2 is MemClk | |
397 | * [18] 0 - K2RUN: disable SDCLK2 | |
398 | * [17] 0 - K1DB2: SDCLK1 is MemClk | |
399 | * [16] 1 - K1RUN: enable SDCLK1 | |
400 | * [15] 1 - E1PIN: SDRAM clock enable | |
401 | * [14] 1 - K0DB2: SDCLK0 is MemClk | |
402 | * [13] 0 - K0RUN: disable SDCLK0 | |
403 | * [12] 1 - E0PIN: disable SDCKE0 | |
404 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | |
405 | */ | |
6d0f6bcf | 406 | #define CONFIG_SYS_MDREFR_VAL 0x0081D018 |
993cad93 WD |
407 | |
408 | /* MDMRS: Mode Register Set Configuration Register | |
409 | * | |
410 | * [31] 0 - reserved | |
411 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | |
412 | * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) | |
413 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | |
414 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | |
415 | * [15] 0 - reserved | |
416 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | |
417 | * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. | |
418 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | |
419 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | |
420 | */ | |
6d0f6bcf | 421 | #define CONFIG_SYS_MDMRS_VAL 0x00020022 |
993cad93 WD |
422 | |
423 | /* | |
424 | * PCMCIA and CF Interfaces | |
425 | */ | |
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
427 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 | |
428 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 | |
429 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 | |
430 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 | |
431 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 | |
432 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 | |
993cad93 WD |
433 | #endif |
434 | ||
435 | /* | |
436 | * GPIO settings | |
437 | */ | |
6d0f6bcf JCPV |
438 | #define CONFIG_SYS_GPSR0_VAL 0xFFFFFFFF |
439 | #define CONFIG_SYS_GPSR1_VAL 0xFFFFFFFF | |
440 | #define CONFIG_SYS_GPSR2_VAL 0xFFFFFFFF | |
441 | #define CONFIG_SYS_GPCR0_VAL 0x08022080 | |
442 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
443 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
444 | #define CONFIG_SYS_GPDR0_VAL 0xCD82A878 | |
445 | #define CONFIG_SYS_GPDR1_VAL 0xFCFFAB80 | |
446 | #define CONFIG_SYS_GPDR2_VAL 0x0001FFFF | |
447 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 | |
448 | #define CONFIG_SYS_GAFR0_U_VAL 0xA5254010 | |
449 | #define CONFIG_SYS_GAFR1_L_VAL 0x599A9550 | |
450 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA | |
451 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA | |
452 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | |
993cad93 | 453 | |
fe8c2806 WD |
454 | /* FIXME: set GPIO_RER/FER */ |
455 | ||
6d0f6bcf | 456 | #define CONFIG_SYS_PSSR_VAL 0x20 |
fe8c2806 WD |
457 | |
458 | /* | |
459 | * Memory settings | |
460 | */ | |
993cad93 | 461 | |
6d0f6bcf JCPV |
462 | #define CONFIG_SYS_MSC0_VAL 0x2ef15af0 |
463 | #define CONFIG_SYS_MSC1_VAL 0x00003ff4 | |
464 | #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 | |
465 | #define CONFIG_SYS_MDCNFG_VAL 0x09a909a9 | |
466 | #define CONFIG_SYS_MDREFR_VAL 0x038ff030 | |
467 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
fe8c2806 WD |
468 | |
469 | /* | |
470 | * PCMCIA and CF Interfaces | |
471 | */ | |
6d0f6bcf JCPV |
472 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
473 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 | |
474 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 | |
475 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 | |
476 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 | |
477 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 | |
478 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 | |
fe8c2806 | 479 | |
384ae025 WD |
480 | #define CSB226_USER_LED0 0x00000008 |
481 | #define CSB226_USER_LED1 0x00000010 | |
482 | #define CSB226_USER_LED2 0x00000020 | |
483 | ||
fe8c2806 WD |
484 | |
485 | /* | |
486 | * FLASH and environment organization | |
487 | */ | |
6d0f6bcf JCPV |
488 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
489 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ | |
fe8c2806 WD |
490 | |
491 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
492 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
493 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
fe8c2806 | 494 | |
5a1aceb0 | 495 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 496 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) |
fe8c2806 | 497 | /* Addr of Environment Sector */ |
0e8d1586 | 498 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
fe8c2806 WD |
499 | |
500 | #endif /* __CONFIG_H */ |