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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. | |
4 | * | |
5 | * Configuration for the Cogent CSB226 board. For details see | |
6 | * http://www.cogcomp.com/csb_csb226.htm | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * include/configs/csb226.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
699b13a6 WD |
34 | #define DEBUG 1 |
35 | ||
fe8c2806 WD |
36 | /* |
37 | * High Level Configuration Options | |
38 | * (easy to change) | |
39 | */ | |
53677ef1 | 40 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
fe8c2806 WD |
41 | #define CONFIG_CSB226 1 /* on a CSB226 board */ |
42 | ||
43 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
44 | /* for timer/console/ethernet */ | |
b3acb6cd JCPV |
45 | |
46 | /* we will never enable dcache, because we have to setup MMU first */ | |
47 | #define CONFIG_SYS_NO_DCACHE | |
38f8eb33 | 48 | #define CONFIG_SYS_TEXT_BASE 0x0 |
fe8c2806 WD |
49 | /* |
50 | * Hardware drivers | |
51 | */ | |
52 | ||
53 | /* | |
54 | * select serial console configuration | |
55 | */ | |
379be585 | 56 | #define CONFIG_PXA_SERIAL |
47cd00fa | 57 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ |
fe8c2806 WD |
58 | |
59 | /* allow to overwrite serial and ethaddr */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
61 | ||
62 | #define CONFIG_BAUDRATE 19200 | |
47cd00fa | 63 | #undef CONFIG_MISC_INIT_R /* not used yet */ |
fe8c2806 | 64 | |
fe8c2806 | 65 | |
80ff4f99 JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_BOOTFILESIZE | |
70 | #define CONFIG_BOOTP_BOOTPATH | |
71 | #define CONFIG_BOOTP_GATEWAY | |
72 | #define CONFIG_BOOTP_HOSTNAME | |
73 | ||
74 | ||
37e4f24b JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
80 | #define CONFIG_CMD_BDI | |
81 | #define CONFIG_CMD_LOADB | |
82 | #define CONFIG_CMD_IMI | |
83 | #define CONFIG_CMD_FLASH | |
84 | #define CONFIG_CMD_MEMORY | |
85 | #define CONFIG_CMD_NET | |
bdab39d3 | 86 | #define CONFIG_CMD_SAVEENV |
37e4f24b JL |
87 | #define CONFIG_CMD_RUN |
88 | #define CONFIG_CMD_ASKENV | |
89 | #define CONFIG_CMD_ECHO | |
90 | #define CONFIG_CMD_DHCP | |
91 | #define CONFIG_CMD_CACHE | |
92 | ||
fe8c2806 | 93 | |
699b13a6 | 94 | #define CONFIG_BOOTDELAY 3 |
993cad93 | 95 | #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" |
fe8c2806 WD |
96 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF |
97 | #define CONFIG_NETMASK 255.255.255.0 | |
98 | #define CONFIG_IPADDR 192.168.1.56 | |
993cad93 | 99 | #define CONFIG_SERVERIP 192.168.1.5 |
699b13a6 | 100 | #define CONFIG_BOOTCOMMAND "bootm 0x40000" |
384ae025 | 101 | #define CONFIG_SHOW_BOOT_PROGRESS |
fe8c2806 | 102 | |
47cd00fa WD |
103 | #define CONFIG_CMDLINE_TAG 1 |
104 | ||
37e4f24b | 105 | #if defined(CONFIG_CMD_KGDB) |
47cd00fa | 106 | #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ |
fe8c2806 WD |
107 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
108 | #endif | |
109 | ||
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
113 | ||
114 | /* | |
115 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
116 | * used for the RAM copy of the uboot code | |
117 | * | |
118 | */ | |
6d0f6bcf | 119 | #define CONFIG_SYS_MALLOC_LEN (128*1024) |
fe8c2806 | 120 | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
122 | #define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ | |
123 | #define CONFIG_SYS_CBSIZE 128 /* Console I/O Buffer Size */ | |
124 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
125 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
126 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
fe8c2806 | 127 | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
129 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
fe8c2806 | 130 | |
6d0f6bcf | 131 | #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ |
fe8c2806 WD |
132 | /* RS: where is this documented? */ |
133 | /* RS: is this where U-Boot is */ | |
134 | /* RS: relocated to in RAM? */ | |
135 | ||
94a33129 | 136 | #define CONFIG_SYS_HZ 1000 |
fe8c2806 | 137 | /* RS: the oscillator is actually 3680130?? */ |
6d0f6bcf | 138 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
fe8c2806 WD |
139 | /* 0101000001 */ |
140 | /* ^^^^^ Memory Speed 99.53 MHz */ | |
141 | /* ^^ Run Mode Speed = 2x Mem Speed */ | |
142 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ | |
143 | ||
6d0f6bcf | 144 | #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ |
fe8c2806 | 145 | |
8bde7f77 | 146 | /* valid baudrates */ |
6d0f6bcf | 147 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
fe8c2806 | 148 | |
993cad93 WD |
149 | /* |
150 | * Network chip | |
151 | */ | |
b1c0eaac BW |
152 | #define CONFIG_NET_MULTI |
153 | #define CONFIG_CS8900 | |
154 | #define CONFIG_CS8900_BUS32 | |
155 | #define CONFIG_CS8900_BASE 0x08000000 | |
993cad93 | 156 | |
fe8c2806 WD |
157 | /* |
158 | * Stack sizes | |
159 | * | |
160 | * The stack sizes are set up in start.S using the settings below | |
161 | */ | |
162 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
163 | #ifdef CONFIG_USE_IRQ | |
164 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
165 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
166 | #endif | |
167 | ||
168 | /* | |
169 | * Physical Memory Map | |
170 | */ | |
171 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
172 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
173 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
174 | ||
175 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
176 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
177 | ||
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* RAM starts here */ |
179 | #define CONFIG_SYS_DRAM_SIZE 0x02000000 | |
fe8c2806 | 180 | |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
fe8c2806 | 182 | |
6ef6eb91 | 183 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
25ddd1fb | 184 | #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1) |
6ef6eb91 | 185 | |
993cad93 WD |
186 | # if 0 |
187 | /* FIXME: switch to _documented_ registers */ | |
fe8c2806 WD |
188 | /* |
189 | * GPIO settings | |
993cad93 WD |
190 | * |
191 | * GP15 == nCS1 is 1 | |
192 | * GP24 == SFRM is 1 | |
193 | * GP25 == TXD is 1 | |
194 | * GP33 == nCS5 is 1 | |
195 | * GP39 == FFTXD is 1 | |
196 | * GP41 == RTS is 1 | |
197 | * GP47 == TXD is 1 | |
198 | * GP49 == nPWE is 1 | |
199 | * GP62 == LED_B is 1 | |
200 | * GP63 == TDM_OE is 1 | |
201 | * GP78 == nCS2 is 1 | |
202 | * GP79 == nCS3 is 1 | |
203 | * GP80 == nCS4 is 1 | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_GPSR0_VAL 0x03008000 |
206 | #define CONFIG_SYS_GPSR1_VAL 0xC0028282 | |
207 | #define CONFIG_SYS_GPSR2_VAL 0x0001C000 | |
993cad93 WD |
208 | |
209 | /* GP02 == DON_RST is 0 | |
210 | * GP23 == SCLK is 0 | |
211 | * GP45 == USB_ACT is 0 | |
212 | * GP60 == PLLEN is 0 | |
213 | * GP61 == LED_A is 0 | |
214 | * GP73 == SWUPD_LED is 0 | |
215 | */ | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_GPCR0_VAL 0x00800004 |
217 | #define CONFIG_SYS_GPCR1_VAL 0x30002000 | |
218 | #define CONFIG_SYS_GPCR2_VAL 0x00000100 | |
993cad93 WD |
219 | |
220 | /* GP00 == DON_READY is input | |
221 | * GP01 == DON_OK is input | |
222 | * GP02 == DON_RST is output | |
223 | * GP03 == RESET_IND is input | |
224 | * GP07 == RES11 is input | |
225 | * GP09 == RES12 is input | |
226 | * GP11 == SWUPDATE is input | |
227 | * GP14 == nPOWEROK is input | |
228 | * GP15 == nCS1 is output | |
229 | * GP17 == RES22 is input | |
230 | * GP18 == RDY is input | |
231 | * GP23 == SCLK is output | |
232 | * GP24 == SFRM is output | |
233 | * GP25 == TXD is output | |
234 | * GP26 == RXD is input | |
235 | * GP32 == RES21 is input | |
236 | * GP33 == nCS5 is output | |
237 | * GP34 == FFRXD is input | |
238 | * GP35 == CTS is input | |
239 | * GP39 == FFTXD is output | |
240 | * GP41 == RTS is output | |
241 | * GP42 == USB_OK is input | |
242 | * GP45 == USB_ACT is output | |
243 | * GP46 == RXD is input | |
244 | * GP47 == TXD is output | |
245 | * GP49 == nPWE is output | |
246 | * GP58 == nCPUBUSINT is input | |
247 | * GP59 == LANINT is input | |
248 | * GP60 == PLLEN is output | |
249 | * GP61 == LED_A is output | |
250 | * GP62 == LED_B is output | |
251 | * GP63 == TDM_OE is output | |
252 | * GP64 == nDSPINT is input | |
253 | * GP65 == STRAP0 is input | |
254 | * GP67 == STRAP1 is input | |
255 | * GP69 == STRAP2 is input | |
256 | * GP70 == STRAP3 is input | |
257 | * GP71 == STRAP4 is input | |
258 | * GP73 == SWUPD_LED is output | |
259 | * GP78 == nCS2 is output | |
260 | * GP79 == nCS3 is output | |
261 | * GP80 == nCS4 is output | |
262 | */ | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_GPDR0_VAL 0x03808004 |
264 | #define CONFIG_SYS_GPDR1_VAL 0xF002A282 | |
265 | #define CONFIG_SYS_GPDR2_VAL 0x0001C200 | |
993cad93 WD |
266 | |
267 | /* GP15 == nCS1 is AF10 | |
268 | * GP18 == RDY is AF01 | |
269 | * GP23 == SCLK is AF10 | |
270 | * GP24 == SFRM is AF10 | |
271 | * GP25 == TXD is AF10 | |
272 | * GP26 == RXD is AF01 | |
273 | * GP33 == nCS5 is AF10 | |
274 | * GP34 == FFRXD is AF01 | |
275 | * GP35 == CTS is AF01 | |
276 | * GP39 == FFTXD is AF10 | |
277 | * GP41 == RTS is AF10 | |
278 | * GP46 == RXD is AF10 | |
279 | * GP47 == TXD is AF01 | |
280 | * GP49 == nPWE is AF10 | |
281 | * GP78 == nCS2 is AF10 | |
282 | * GP79 == nCS3 is AF10 | |
283 | * GP80 == nCS4 is AF10 | |
fe8c2806 | 284 | */ |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 |
286 | #define CONFIG_SYS_GAFR0_U_VAL 0x001A8010 | |
287 | #define CONFIG_SYS_GAFR1_L_VAL 0x60088058 | |
288 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 | |
289 | #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 | |
290 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | |
fe8c2806 | 291 | |
993cad93 WD |
292 | |
293 | /* FIXME: set GPIO_RER/FER */ | |
294 | ||
295 | /* RDH = 1 | |
296 | * PH = 1 | |
297 | * VFS = 1 | |
298 | * BFS = 1 | |
299 | * SSS = 1 | |
300 | */ | |
6d0f6bcf | 301 | #define CONFIG_SYS_PSSR_VAL 0x37 |
993cad93 WD |
302 | |
303 | /* | |
304 | * Memory settings | |
305 | * | |
306 | * This is the configuration for nCS0/1 -> flash banks | |
307 | * configuration for nCS1: | |
308 | * [31] 0 - Slower Device | |
309 | * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
310 | * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
311 | * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
312 | * [19] 1 - 16 Bit bus width | |
313 | * [18:16] 000 - nonburst RAM or FLASH | |
314 | * configuration for nCS0: | |
315 | * [15] 0 - Slower Device | |
316 | * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
317 | * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
318 | * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
319 | * [03] 1 - 16 Bit bus width | |
320 | * [02:00] 000 - nonburst RAM or FLASH | |
321 | */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_MSC0_VAL 0x25b825b8 /* flash banks */ |
993cad93 WD |
323 | |
324 | /* This is the configuration for nCS2/3 -> TDM-Switch, DSP | |
325 | * configuration for nCS3: DSP | |
326 | * [31] 0 - Slower Device | |
327 | * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
328 | * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
329 | * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns | |
330 | * [19] 1 - 16 Bit bus width | |
331 | * [18:16] 100 - variable latency I/O | |
332 | * configuration for nCS2: TDM-Switch | |
333 | * [15] 0 - Slower Device | |
334 | * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns | |
335 | * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns | |
336 | * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns | |
337 | * [03] 1 - 16 Bit bus width | |
338 | * [02:00] 100 - variable latency I/O | |
339 | */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_MSC1_VAL 0x123C593C /* TDM switch, DSP */ |
993cad93 WD |
341 | |
342 | /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller | |
343 | * | |
344 | * configuration for nCS5: LAN Controller | |
345 | * [31] 0 - Slower Device | |
346 | * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
347 | * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
348 | * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns | |
349 | * [19] 1 - 16 Bit bus width | |
350 | * [18:16] 100 - variable latency I/O | |
351 | * configuration for nCS4: ExtBus | |
352 | * [15] 0 - Slower Device | |
353 | * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns | |
354 | * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns | |
355 | * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns | |
356 | * [03] 1 - 16 Bit bus width | |
357 | * [02:00] 100 - variable latency I/O | |
358 | */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ |
993cad93 WD |
360 | |
361 | /* MDCNFG: SDRAM Configuration Register | |
362 | * | |
363 | * [31:29] 000 - reserved | |
364 | * [28] 0 - no SA1111 compatiblity mode | |
365 | * [27] 0 - latch return data with return clock | |
366 | * [26] 0 - alternate addressing for pair 2/3 | |
367 | * [25:24] 00 - timings | |
368 | * [23] 0 - internal banks in lower partition 2/3 (not used) | |
369 | * [22:21] 00 - row address bits for partition 2/3 (not used) | |
370 | * [20:19] 00 - column address bits for partition 2/3 (not used) | |
371 | * [18] 0 - SDRAM partition 2/3 width is 32 bit | |
372 | * [17] 0 - SDRAM partition 3 disabled | |
373 | * [16] 0 - SDRAM partition 2 disabled | |
374 | * [15:13] 000 - reserved | |
375 | * [12] 1 - SA1111 compatiblity mode | |
376 | * [11] 1 - latch return data with return clock | |
377 | * [10] 0 - no alternate addressing for pair 0/1 | |
378 | * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk | |
379 | * [7] 1 - 4 internal banks in lower partition pair | |
380 | * [06:05] 10 - 13 row address bits for partition 0/1 | |
381 | * [04:03] 01 - 9 column address bits for partition 0/1 | |
382 | * [02] 0 - SDRAM partition 0/1 width is 32 bit | |
383 | * [01] 0 - disable SDRAM partition 1 | |
384 | * [00] 1 - enable SDRAM partition 0 | |
385 | */ | |
386 | /* use the configuration above but disable partition 0 */ | |
6d0f6bcf | 387 | #define CONFIG_SYS_MDCNFG_VAL 0x000019c8 |
993cad93 WD |
388 | |
389 | /* MDREFR: SDRAM Refresh Control Register | |
390 | * | |
391 | * [32:26] 0 - reserved | |
392 | * [25] 0 - K2FREE: not free running | |
393 | * [24] 0 - K1FREE: not free running | |
394 | * [23] 1 - K0FREE: not free running | |
395 | * [22] 0 - SLFRSH: self refresh disabled | |
396 | * [21] 0 - reserved | |
397 | * [20] 0 - APD: no auto power down | |
398 | * [19] 0 - K2DB2: SDCLK2 is MemClk | |
399 | * [18] 0 - K2RUN: disable SDCLK2 | |
400 | * [17] 0 - K1DB2: SDCLK1 is MemClk | |
401 | * [16] 1 - K1RUN: enable SDCLK1 | |
402 | * [15] 1 - E1PIN: SDRAM clock enable | |
403 | * [14] 1 - K0DB2: SDCLK0 is MemClk | |
404 | * [13] 0 - K0RUN: disable SDCLK0 | |
405 | * [12] 1 - E0PIN: disable SDCKE0 | |
406 | * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | |
407 | */ | |
6d0f6bcf | 408 | #define CONFIG_SYS_MDREFR_VAL 0x0081D018 |
993cad93 WD |
409 | |
410 | /* MDMRS: Mode Register Set Configuration Register | |
411 | * | |
412 | * [31] 0 - reserved | |
413 | * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | |
414 | * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) | |
415 | * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | |
416 | * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | |
417 | * [15] 0 - reserved | |
418 | * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | |
419 | * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. | |
420 | * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | |
421 | * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | |
422 | */ | |
6d0f6bcf | 423 | #define CONFIG_SYS_MDMRS_VAL 0x00020022 |
993cad93 WD |
424 | |
425 | /* | |
426 | * PCMCIA and CF Interfaces | |
427 | */ | |
6d0f6bcf JCPV |
428 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
429 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 | |
430 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 | |
431 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 | |
432 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 | |
433 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 | |
434 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 | |
993cad93 WD |
435 | #endif |
436 | ||
437 | /* | |
438 | * GPIO settings | |
439 | */ | |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_GPSR0_VAL 0xFFFFFFFF |
441 | #define CONFIG_SYS_GPSR1_VAL 0xFFFFFFFF | |
442 | #define CONFIG_SYS_GPSR2_VAL 0xFFFFFFFF | |
443 | #define CONFIG_SYS_GPCR0_VAL 0x08022080 | |
444 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
445 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
446 | #define CONFIG_SYS_GPDR0_VAL 0xCD82A878 | |
447 | #define CONFIG_SYS_GPDR1_VAL 0xFCFFAB80 | |
448 | #define CONFIG_SYS_GPDR2_VAL 0x0001FFFF | |
449 | #define CONFIG_SYS_GAFR0_L_VAL 0x80000000 | |
450 | #define CONFIG_SYS_GAFR0_U_VAL 0xA5254010 | |
451 | #define CONFIG_SYS_GAFR1_L_VAL 0x599A9550 | |
452 | #define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA | |
453 | #define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA | |
454 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 | |
993cad93 | 455 | |
fe8c2806 WD |
456 | /* FIXME: set GPIO_RER/FER */ |
457 | ||
6d0f6bcf | 458 | #define CONFIG_SYS_PSSR_VAL 0x20 |
fe8c2806 | 459 | |
eb0e11bd MV |
460 | #define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 |
461 | #define CONFIG_SYS_CKEN 0x0 | |
462 | ||
fe8c2806 WD |
463 | /* |
464 | * Memory settings | |
465 | */ | |
993cad93 | 466 | |
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_MSC0_VAL 0x2ef15af0 |
468 | #define CONFIG_SYS_MSC1_VAL 0x00003ff4 | |
469 | #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 | |
470 | #define CONFIG_SYS_MDCNFG_VAL 0x09a909a9 | |
471 | #define CONFIG_SYS_MDREFR_VAL 0x038ff030 | |
472 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
38f8eb33 MV |
473 | #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 |
474 | #define CONFIG_SYS_SXCNFG_VAL 0x00000000 | |
fe8c2806 WD |
475 | |
476 | /* | |
477 | * PCMCIA and CF Interfaces | |
478 | */ | |
6d0f6bcf JCPV |
479 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
480 | #define CONFIG_SYS_MCMEM0_VAL 0x00000000 | |
481 | #define CONFIG_SYS_MCMEM1_VAL 0x00000000 | |
482 | #define CONFIG_SYS_MCATT0_VAL 0x00000000 | |
483 | #define CONFIG_SYS_MCATT1_VAL 0x00000000 | |
484 | #define CONFIG_SYS_MCIO0_VAL 0x00000000 | |
485 | #define CONFIG_SYS_MCIO1_VAL 0x00000000 | |
fe8c2806 | 486 | |
384ae025 WD |
487 | #define CSB226_USER_LED0 0x00000008 |
488 | #define CSB226_USER_LED1 0x00000010 | |
489 | #define CSB226_USER_LED2 0x00000020 | |
490 | ||
fe8c2806 WD |
491 | |
492 | /* | |
493 | * FLASH and environment organization | |
494 | */ | |
6d0f6bcf JCPV |
495 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
496 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ | |
fe8c2806 WD |
497 | |
498 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
499 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
500 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
fe8c2806 | 501 | |
5a1aceb0 | 502 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 503 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) |
fe8c2806 | 504 | /* Addr of Environment Sector */ |
0e8d1586 | 505 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
fe8c2806 WD |
506 | |
507 | #endif /* __CONFIG_H */ |