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1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. | |
4 | * | |
5 | * Configuration for the Cogent CSB226 board. For details see | |
6 | * http://www.cogcomp.com/csb_csb226.htm | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * include/configs/csb226.h - configuration options, board specific | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /* | |
35 | * If we are developing, we might want to start U-Boot from ram | |
36 | * so we MUST NOT initialize critical regs like mem-timing ... | |
37 | */ | |
38 | #define CONFIG_INIT_CRITICAL /* undef for developing */ | |
39 | ||
40 | /* | |
41 | * High Level Configuration Options | |
42 | * (easy to change) | |
43 | */ | |
44 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
45 | #define CONFIG_CSB226 1 /* on a CSB226 board */ | |
46 | ||
47 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
48 | /* for timer/console/ethernet */ | |
49 | /* | |
50 | * Hardware drivers | |
51 | */ | |
52 | ||
53 | /* | |
54 | * select serial console configuration | |
55 | */ | |
56 | #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ | |
57 | ||
58 | /* allow to overwrite serial and ethaddr */ | |
59 | #define CONFIG_ENV_OVERWRITE | |
60 | ||
61 | #define CONFIG_BAUDRATE 19200 | |
62 | ||
63 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) | |
64 | ||
65 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
66 | #include <cmd_confdefs.h> | |
67 | ||
68 | #define CONFIG_BOOTDELAY 10 | |
69 | #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" | |
70 | #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF | |
71 | #define CONFIG_NETMASK 255.255.255.0 | |
72 | #define CONFIG_IPADDR 192.168.1.56 | |
73 | #define CONFIG_SERVERIP 192.168.1.2 | |
74 | #define CONFIG_BOOTCOMMAND "" | |
75 | ||
76 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
77 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ | |
78 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
79 | #endif | |
80 | ||
81 | /* | |
82 | * Miscellaneous configurable options | |
83 | */ | |
84 | ||
85 | /* | |
86 | * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
87 | * used for the RAM copy of the uboot code | |
88 | * | |
89 | */ | |
90 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) | |
91 | ||
92 | #define CFG_LONGHELP /* undef to save memory */ | |
93 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
94 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
95 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
96 | #define CFG_MAXARGS 16 /* max number of command args */ | |
97 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
98 | ||
99 | #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ | |
100 | #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
101 | ||
102 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
103 | ||
104 | #define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */ | |
105 | /* RS: where is this documented? */ | |
106 | /* RS: is this where U-Boot is */ | |
107 | /* RS: relocated to in RAM? */ | |
108 | ||
109 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
110 | /* RS: the oscillator is actually 3680130?? */ | |
111 | #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ | |
112 | /* 0101000001 */ | |
113 | /* ^^^^^ Memory Speed 99.53 MHz */ | |
114 | /* ^^ Run Mode Speed = 2x Mem Speed */ | |
115 | /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ | |
116 | ||
117 | #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ | |
118 | ||
119 | /* valid baudrates */ | |
120 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
121 | ||
122 | /* | |
123 | * Stack sizes | |
124 | * | |
125 | * The stack sizes are set up in start.S using the settings below | |
126 | */ | |
127 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
128 | #ifdef CONFIG_USE_IRQ | |
129 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
130 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
131 | #endif | |
132 | ||
133 | /* | |
134 | * Physical Memory Map | |
135 | */ | |
136 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
137 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
138 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
139 | ||
140 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
141 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
142 | ||
143 | #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ | |
144 | #define CFG_DRAM_SIZE 0x02000000 | |
145 | ||
146 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
147 | ||
148 | /* | |
149 | * GPIO settings | |
150 | */ | |
151 | #define CFG_GPSR0_VAL 0xFFFFFFFF | |
152 | #define CFG_GPSR1_VAL 0xFFFFFFFF | |
153 | #define CFG_GPSR2_VAL 0xFFFFFFFF | |
154 | #define CFG_GPCR0_VAL 0x08022080 | |
155 | #define CFG_GPCR1_VAL 0x00000000 | |
156 | #define CFG_GPCR2_VAL 0x00000000 | |
157 | #define CFG_GPDR0_VAL 0xCD82A858 | |
158 | #define CFG_GPDR1_VAL 0xFCFFAB80 | |
159 | #define CFG_GPDR2_VAL 0x0001FFFF | |
160 | #define CFG_GAFR0_L_VAL 0x80000000 | |
161 | #define CFG_GAFR0_U_VAL 0xA5254010 | |
162 | #define CFG_GAFR1_L_VAL 0x599A9550 | |
163 | #define CFG_GAFR1_U_VAL 0xAAA5AAAA | |
164 | #define CFG_GAFR2_L_VAL 0xAAAAAAAA | |
165 | #define CFG_GAFR2_U_VAL 0x00000002 | |
166 | ||
167 | /* FIXME: set GPIO_RER/FER */ | |
168 | ||
169 | #define CFG_PSSR_VAL 0x20 | |
170 | ||
171 | /* | |
172 | * Memory settings | |
173 | */ | |
174 | #define CFG_MSC0_VAL 0x2EF025D0 | |
175 | #define CFG_MSC1_VAL 0x00003F64 | |
176 | #define CFG_MSC2_VAL 0x00000000 | |
177 | #define CFG_MDCNFG_VAL 0x09a909a9 | |
178 | #define CFG_MDREFR_VAL 0x03ca0030 | |
179 | /* #define CFG_MDREFR_VAL_100 ??? */ | |
180 | #define CFG_MDMRS_VAL 0x00220022 | |
181 | ||
182 | /* | |
183 | * PCMCIA and CF Interfaces | |
184 | */ | |
185 | #define CFG_MECR_VAL 0x00000000 | |
186 | #define CFG_MCMEM0_VAL 0x00000000 | |
187 | #define CFG_MCMEM1_VAL 0x00000000 | |
188 | #define CFG_MCATT0_VAL 0x00000000 | |
189 | #define CFG_MCATT1_VAL 0x00000000 | |
190 | #define CFG_MCIO0_VAL 0x00000000 | |
191 | #define CFG_MCIO1_VAL 0x00000000 | |
192 | ||
193 | /* | |
194 | #define _LED 0x08000010 | |
195 | #define LED_BLANK (0x08000040) | |
196 | */ | |
197 | ||
198 | /* | |
199 | * FLASH and environment organization | |
200 | */ | |
201 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
202 | #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ | |
203 | ||
204 | /* timeout values are in ticks */ | |
205 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ | |
206 | #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ | |
207 | ||
208 | #define CFG_ENV_IS_IN_FLASH 1 | |
209 | #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) | |
210 | /* Addr of Environment Sector */ | |
211 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
212 | ||
213 | #endif /* __CONFIG_H */ |