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87e29878 AF |
1 | /* |
2 | * Based on corenet_ds.h | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
87e29878 AF |
10 | #define CONFIG_CYRUS |
11 | ||
cefe11cd | 12 | #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_PPC_P5040) |
87e29878 AF |
13 | #error Must call Cyrus CONFIG with a specific CPU enabled. |
14 | #endif | |
15 | ||
87e29878 AF |
16 | #define CONFIG_MMC |
17 | #define CONFIG_SDCARD | |
18 | #define CONFIG_FSL_SATA_V2 | |
19 | #define CONFIG_PCIE3 | |
20 | #define CONFIG_PCIE4 | |
cefe11cd | 21 | #ifdef CONFIG_ARCH_P5020 |
87e29878 AF |
22 | #define CONFIG_SYS_FSL_RAID_ENGINE |
23 | #define CONFIG_SYS_DPAA_RMAN | |
24 | #endif | |
25 | #define CONFIG_SYS_DPAA_PME | |
26 | ||
27 | /* | |
28 | * Corenet DS style board configuration file | |
29 | */ | |
30 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
31 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
32 | #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg | |
cefe11cd | 33 | #if defined(CONFIG_ARCH_P5020) |
87e29878 AF |
34 | #define CONFIG_SYS_CLK_FREQ 133000000 |
35 | #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg | |
36 | #elif defined(CONFIG_PPC_P5040) | |
37 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
38 | #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg | |
39 | #endif | |
40 | ||
87e29878 AF |
41 | /* High Level Configuration Options */ |
42 | #define CONFIG_BOOKE | |
43 | #define CONFIG_E500 /* BOOKE e500 family */ | |
44 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
45 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
46 | #define CONFIG_MP /* support multiple processors */ | |
47 | ||
87e29878 AF |
48 | #define CONFIG_SYS_MMC_MAX_DEVICE 1 |
49 | ||
50 | #ifndef CONFIG_SYS_TEXT_BASE | |
51 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
52 | #endif | |
53 | ||
54 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
55 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
56 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
b38eaec5 RD |
57 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
58 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
87e29878 AF |
59 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
60 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
61 | ||
62 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
63 | ||
64 | #define CONFIG_ENV_OVERWRITE | |
65 | ||
66 | #define CONFIG_SYS_NO_FLASH | |
67 | ||
68 | #if defined(CONFIG_SDCARD) | |
69 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
70 | #define CONFIG_ENV_IS_IN_MMC | |
71 | #define CONFIG_FSL_FIXED_MMC_LOCATION | |
72 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
73 | #define CONFIG_ENV_SIZE 0x2000 | |
74 | #define CONFIG_ENV_OFFSET (512 * 1658) | |
75 | #endif | |
76 | ||
77 | /* | |
78 | * These can be toggled for performance analysis, otherwise use default. | |
79 | */ | |
80 | #define CONFIG_SYS_CACHE_STASHING | |
81 | #define CONFIG_BACKSIDE_L2_CACHE | |
82 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
83 | #define CONFIG_BTB /* toggle branch predition */ | |
84 | #define CONFIG_DDR_ECC | |
85 | #ifdef CONFIG_DDR_ECC | |
86 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
87 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
88 | #endif | |
89 | ||
90 | #define CONFIG_ENABLE_36BIT_PHYS | |
91 | ||
92 | #ifdef CONFIG_PHYS_64BIT | |
93 | #define CONFIG_ADDR_MAP | |
94 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
95 | #endif | |
96 | ||
97 | /* test POST memory test */ | |
98 | #undef CONFIG_POST | |
99 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
100 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
101 | #define CONFIG_SYS_ALT_MEMTEST | |
102 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
103 | ||
104 | /* | |
105 | * Config the L3 Cache as L3 SRAM | |
106 | */ | |
107 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
108 | #ifdef CONFIG_PHYS_64BIT | |
109 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
110 | #else | |
111 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
112 | #endif | |
113 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
114 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
115 | ||
116 | #ifdef CONFIG_PHYS_64BIT | |
117 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
118 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
119 | #endif | |
120 | ||
121 | /* | |
122 | * DDR Setup | |
123 | */ | |
124 | #define CONFIG_VERY_BIG_RAM | |
125 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
126 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
127 | ||
128 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
129 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
130 | ||
131 | #define CONFIG_DDR_SPD | |
132 | #define CONFIG_SYS_FSL_DDR3 | |
133 | ||
134 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
135 | #define SPD_EEPROM_ADDRESS1 0x51 | |
136 | #define SPD_EEPROM_ADDRESS2 0x52 | |
137 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
138 | ||
139 | /* | |
140 | * Local Bus Definitions | |
141 | */ | |
142 | ||
143 | #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ | |
144 | #ifdef CONFIG_PHYS_64BIT | |
145 | #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull | |
146 | #else | |
147 | #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE | |
148 | #endif | |
149 | ||
150 | #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ | |
151 | #ifdef CONFIG_PHYS_64BIT | |
152 | #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull | |
153 | #else | |
154 | #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE | |
155 | #endif | |
156 | ||
157 | /* Set the local bus clock 1/16 of platform clock */ | |
158 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) | |
159 | ||
160 | #define CONFIG_SYS_BR0_PRELIM \ | |
161 | (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) | |
162 | #define CONFIG_SYS_BR1_PRELIM \ | |
163 | (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) | |
164 | ||
165 | #define CONFIG_SYS_OR0_PRELIM 0xfff00010 | |
166 | #define CONFIG_SYS_OR1_PRELIM 0xfff00010 | |
167 | ||
87e29878 AF |
168 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
169 | ||
170 | #if defined(CONFIG_RAMBOOT_PBL) | |
171 | #define CONFIG_SYS_RAMBOOT | |
172 | #endif | |
173 | ||
174 | #define CONFIG_BOARD_EARLY_INIT_F | |
175 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
176 | #define CONFIG_MISC_INIT_R | |
177 | ||
178 | #define CONFIG_HWCONFIG | |
179 | ||
180 | /* define to use L1 as initial stack */ | |
181 | #define CONFIG_L1_INIT_RAM | |
182 | #define CONFIG_SYS_INIT_RAM_LOCK | |
183 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
184 | #ifdef CONFIG_PHYS_64BIT | |
185 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
186 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
187 | /* The assembler doesn't like typecast */ | |
188 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
189 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
190 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
191 | #else | |
192 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
193 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
194 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
195 | #endif | |
196 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ | |
197 | ||
198 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
199 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
200 | ||
201 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) | |
202 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
203 | ||
204 | /* Serial Port - controlled on board with jumper J8 | |
205 | * open - index 2 | |
206 | * shorted - index 1 | |
207 | */ | |
208 | #define CONFIG_CONS_INDEX 1 | |
87e29878 AF |
209 | #define CONFIG_SYS_NS16550_SERIAL |
210 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
211 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
212 | ||
213 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
214 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
215 | ||
216 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
217 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
218 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
219 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
220 | ||
87e29878 AF |
221 | /* I2C */ |
222 | #define CONFIG_SYS_I2C | |
223 | #define CONFIG_SYS_I2C_FSL | |
224 | #define CONFIG_I2C_MULTI_BUS | |
225 | #define CONFIG_I2C_CMD_TREE | |
226 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ | |
227 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
228 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
229 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ | |
230 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
231 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
232 | #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ | |
233 | #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F | |
234 | #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 | |
235 | #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ | |
236 | #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F | |
237 | #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 | |
238 | ||
239 | #define CONFIG_ID_EEPROM | |
240 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
241 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
242 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
243 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
244 | ||
245 | #define CONFIG_SYS_I2C_GENERIC_MAC | |
246 | #define CONFIG_SYS_I2C_MAC1_BUS 3 | |
247 | #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 | |
248 | #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 | |
249 | #define CONFIG_SYS_I2C_MAC2_BUS 0 | |
250 | #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 | |
251 | #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa | |
252 | ||
253 | #define CONFIG_CMD_DATE 1 | |
254 | #define CONFIG_RTC_MCP79411 1 | |
255 | #define CONFIG_SYS_RTC_BUS_NUM 3 | |
256 | #define CONFIG_SYS_I2C_RTC_ADDR 0x6f | |
257 | ||
258 | /* | |
259 | * eSPI - Enhanced SPI | |
260 | */ | |
87e29878 AF |
261 | |
262 | /* | |
263 | * General PCI | |
264 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
265 | */ | |
266 | ||
267 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
268 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
269 | #ifdef CONFIG_PHYS_64BIT | |
270 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
271 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
272 | #else | |
273 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
274 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
275 | #endif | |
276 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
277 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
278 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
279 | #ifdef CONFIG_PHYS_64BIT | |
280 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
281 | #else | |
282 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
283 | #endif | |
284 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
285 | ||
286 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
287 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
288 | #ifdef CONFIG_PHYS_64BIT | |
289 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
290 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
291 | #else | |
292 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
293 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
294 | #endif | |
295 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
296 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
297 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
298 | #ifdef CONFIG_PHYS_64BIT | |
299 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
300 | #else | |
301 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
302 | #endif | |
303 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
304 | ||
305 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
306 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
307 | #ifdef CONFIG_PHYS_64BIT | |
308 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
309 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
310 | #else | |
311 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
312 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
313 | #endif | |
314 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
315 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
316 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
317 | #ifdef CONFIG_PHYS_64BIT | |
318 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
319 | #else | |
320 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
321 | #endif | |
322 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
323 | ||
324 | /* controller 4, Base address 203000 */ | |
325 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
326 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
327 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
328 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
329 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
330 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
331 | ||
332 | /* Qman/Bman */ | |
333 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
334 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 | |
335 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
336 | #ifdef CONFIG_PHYS_64BIT | |
337 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
338 | #else | |
339 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
340 | #endif | |
341 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
342 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 | |
343 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
344 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
345 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
346 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
347 | CONFIG_SYS_BMAN_CENA_SIZE) | |
348 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
349 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
350 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
351 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
352 | #ifdef CONFIG_PHYS_64BIT | |
353 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
354 | #else | |
355 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
356 | #endif | |
357 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
358 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 | |
359 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
360 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
361 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
362 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
363 | CONFIG_SYS_QMAN_CENA_SIZE) | |
364 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
365 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
366 | ||
367 | #define CONFIG_SYS_DPAA_FMAN | |
368 | /* Default address of microcode for the Linux Fman driver */ | |
369 | /* | |
370 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
371 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is | |
372 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
373 | */ | |
374 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
375 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) | |
376 | ||
377 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
378 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
379 | ||
380 | #ifdef CONFIG_SYS_DPAA_FMAN | |
381 | #define CONFIG_FMAN_ENET | |
382 | #define CONFIG_PHY_MICREL | |
383 | #define CONFIG_PHY_MICREL_KSZ9021 | |
384 | #endif | |
385 | ||
386 | #ifdef CONFIG_PCI | |
387 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
87e29878 AF |
388 | #define CONFIG_NET_MULTI |
389 | ||
390 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
391 | #define CONFIG_DOS_PARTITION | |
392 | #endif /* CONFIG_PCI */ | |
393 | ||
394 | /* SATA */ | |
395 | #ifdef CONFIG_FSL_SATA_V2 | |
396 | #define CONFIG_LIBATA | |
397 | #define CONFIG_FSL_SATA | |
398 | ||
399 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
400 | #define CONFIG_SATA1 | |
401 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
402 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
403 | #define CONFIG_SATA2 | |
404 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
405 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
406 | ||
407 | #define CONFIG_LBA48 | |
408 | #define CONFIG_CMD_SATA | |
409 | #define CONFIG_DOS_PARTITION | |
87e29878 AF |
410 | #endif |
411 | ||
412 | #ifdef CONFIG_FMAN_ENET | |
413 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
414 | #define CONFIG_MII /* MII PHY management */ | |
415 | #define CONFIG_ETHPRIME "FM1@DTSEC4" | |
416 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
417 | #endif | |
418 | ||
419 | /* | |
420 | * Environment | |
421 | */ | |
422 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
423 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
424 | ||
425 | /* | |
426 | * Command line configuration. | |
427 | */ | |
87e29878 | 428 | #define CONFIG_CMD_ERRATA |
87e29878 | 429 | #define CONFIG_CMD_IRQ |
87e29878 AF |
430 | #define CONFIG_CMD_REGINFO |
431 | ||
432 | #ifdef CONFIG_PCI | |
433 | #define CONFIG_CMD_PCI | |
434 | #endif | |
435 | ||
436 | /* | |
437 | * USB | |
438 | */ | |
439 | #define CONFIG_HAS_FSL_DR_USB | |
440 | #define CONFIG_HAS_FSL_MPH_USB | |
441 | ||
442 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
87e29878 AF |
443 | #define CONFIG_USB_EHCI |
444 | #define CONFIG_USB_EHCI_FSL | |
445 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
87e29878 | 446 | #define CONFIG_EHCI_IS_TDI |
87e29878 AF |
447 | #define CONFIG_SYS_USB_EVENT_POLL |
448 | /* _VIA_CONTROL_EP */ | |
87e29878 AF |
449 | #endif |
450 | ||
451 | #ifdef CONFIG_MMC | |
452 | #define CONFIG_FSL_ESDHC | |
453 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
454 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
87e29878 | 455 | #define CONFIG_GENERIC_MMC |
87e29878 AF |
456 | #define CONFIG_DOS_PARTITION |
457 | #endif | |
458 | ||
459 | /* | |
460 | * Miscellaneous configurable options | |
461 | */ | |
462 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
463 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
464 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
465 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
87e29878 AF |
466 | #ifdef CONFIG_CMD_KGDB |
467 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
468 | #else | |
469 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
470 | #endif | |
471 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
472 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
473 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
474 | ||
475 | /* | |
476 | * For booting Linux, the board info and command line data | |
477 | * have to be in the first 64 MB of memory, since this is | |
478 | * the maximum mapped by the Linux kernel during initialization. | |
479 | */ | |
480 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ | |
481 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
482 | ||
483 | #ifdef CONFIG_CMD_KGDB | |
484 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
485 | #endif | |
486 | ||
487 | /* | |
488 | * Environment Configuration | |
489 | */ | |
490 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
491 | #define CONFIG_BOOTFILE "uImage" | |
492 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
493 | ||
494 | /* default location for tftp and bootm */ | |
495 | #define CONFIG_LOADADDR 1000000 | |
496 | ||
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497 | |
498 | #define CONFIG_BAUDRATE 115200 | |
499 | ||
500 | #define __USB_PHY_TYPE utmi | |
501 | ||
502 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
503 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ | |
504 | "bank_intlv=cs0_cs1;" \ | |
505 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ | |
506 | "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
507 | "netdev=eth0\0" \ | |
508 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
509 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
510 | "consoledev=ttyS0\0" \ | |
511 | "ramdiskaddr=2000000\0" \ | |
b24a4f62 | 512 | "fdtaddr=1e00000\0" \ |
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513 | "bdev=sda3\0" |
514 | ||
515 | #define CONFIG_HDBOOT \ | |
516 | "setenv bootargs root=/dev/$bdev rw " \ | |
517 | "console=$consoledev,$baudrate $othbootargs;" \ | |
518 | "tftp $loadaddr $bootfile;" \ | |
519 | "tftp $fdtaddr $fdtfile;" \ | |
520 | "bootm $loadaddr - $fdtaddr" | |
521 | ||
522 | #define CONFIG_NFSBOOTCOMMAND \ | |
523 | "setenv bootargs root=/dev/nfs rw " \ | |
524 | "nfsroot=$serverip:$rootpath " \ | |
525 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
526 | "console=$consoledev,$baudrate $othbootargs;" \ | |
527 | "tftp $loadaddr $bootfile;" \ | |
528 | "tftp $fdtaddr $fdtfile;" \ | |
529 | "bootm $loadaddr - $fdtaddr" | |
530 | ||
531 | #define CONFIG_RAMBOOTCOMMAND \ | |
532 | "setenv bootargs root=/dev/ram rw " \ | |
533 | "console=$consoledev,$baudrate $othbootargs;" \ | |
534 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
535 | "tftp $loadaddr $bootfile;" \ | |
536 | "tftp $fdtaddr $fdtfile;" \ | |
537 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
538 | ||
539 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
540 | ||
541 | #include <asm/fsl_secure_boot.h> | |
542 | ||
543 | #ifdef CONFIG_SECURE_BOOT | |
544 | #endif | |
545 | ||
546 | #endif /* __CONFIG_H */ |