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28b00324 DB |
1 | /* |
2 | * Copyright (C) 2009 David Brownell | |
3 | * | |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
28b00324 DB |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
28b00324 DB |
9 | |
10 | /* Spectrum Digital TMS320DM355 EVM board */ | |
11 | #define DAVINCI_DM355EVM | |
12 | ||
13 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ | |
28b00324 DB |
14 | #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ |
15 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
28b00324 DB |
16 | |
17 | /* SoC Configuration */ | |
28b00324 DB |
18 | #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ |
19 | #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ | |
28b00324 DB |
20 | #define CONFIG_SOC_DM355 |
21 | ||
22 | /* Memory Info */ | |
23 | #define CONFIG_NR_DRAM_BANKS 1 | |
24 | #define PHYS_SDRAM_1 0x80000000 | |
a16df2c1 | 25 | #define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ |
28b00324 DB |
26 | |
27 | /* Serial Driver info: UART0 for console */ | |
28 | #define CONFIG_SYS_NS16550 | |
29 | #define CONFIG_SYS_NS16550_SERIAL | |
30 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
31 | #define CONFIG_SYS_NS16550_COM1 0x01c20000 | |
32 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK | |
28b00324 DB |
33 | #define CONFIG_CONS_INDEX 1 |
34 | #define CONFIG_BAUDRATE 115200 | |
35 | ||
36 | /* Ethernet: external DM9000 */ | |
37 | #define CONFIG_DRIVER_DM9000 1 | |
38 | #define CONFIG_DM9000_BASE 0x04014000 | |
39 | #define DM9000_IO CONFIG_DM9000_BASE | |
40 | #define DM9000_DATA (CONFIG_DM9000_BASE + 2) | |
41 | ||
42 | /* I2C */ | |
e8459dcc VA |
43 | #define CONFIG_SYS_I2C |
44 | #define CONFIG_SYS_I2C_DAVINCI | |
45 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 | |
46 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ | |
28b00324 DB |
47 | |
48 | /* NAND: socketed, two chipselects, normally 2 GBytes */ | |
409ec37b | 49 | #define CONFIG_NAND_DAVINCI |
97f4eb8c | 50 | #define CONFIG_SYS_NAND_CS 2 |
28b00324 | 51 | #define CONFIG_SYS_NAND_USE_FLASH_BBT |
409ec37b SP |
52 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
53 | #define CONFIG_SYS_NAND_PAGE_2K | |
28b00324 DB |
54 | |
55 | #define CONFIG_SYS_NAND_LARGEPAGE | |
56 | #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } | |
57 | /* socket has two chipselects, nCE0 gated by address BIT(14) */ | |
58 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
59 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
60 | ||
073eacf0 SP |
61 | /* SD/MMC */ |
62 | #define CONFIG_MMC | |
63 | #define CONFIG_GENERIC_MMC | |
64 | #define CONFIG_DAVINCI_MMC | |
65 | #define CONFIG_DAVINCI_MMC_SD1 | |
66 | #define CONFIG_MMC_MBLOCK | |
67 | ||
28b00324 DB |
68 | /* USB: OTG connector */ |
69 | /* NYET -- #define CONFIG_USB_DAVINCI */ | |
70 | ||
71 | /* U-Boot command configuration */ | |
72 | #include <config_cmd_default.h> | |
73 | ||
74 | #undef CONFIG_CMD_BDI | |
75 | #undef CONFIG_CMD_FLASH | |
76 | #undef CONFIG_CMD_FPGA | |
77 | #undef CONFIG_CMD_SETGETDCR | |
78 | ||
79 | #define CONFIG_CMD_ASKENV | |
80 | #define CONFIG_CMD_DHCP | |
81 | #define CONFIG_CMD_I2C | |
82 | #define CONFIG_CMD_PING | |
83 | #define CONFIG_CMD_SAVES | |
84 | ||
8f5d4687 HM |
85 | #ifdef CONFIG_CMD_BDI |
86 | #define CONFIG_CLOCKS | |
87 | #endif | |
88 | ||
073eacf0 SP |
89 | #ifdef CONFIG_MMC |
90 | #define CONFIG_DOS_PARTITION | |
91 | #define CONFIG_CMD_EXT2 | |
92 | #define CONFIG_CMD_FAT | |
93 | #define CONFIG_CMD_MMC | |
94 | #endif | |
95 | ||
28b00324 DB |
96 | #ifdef CONFIG_NAND_DAVINCI |
97 | #define CONFIG_CMD_MTDPARTS | |
98 | #define CONFIG_MTD_PARTITIONS | |
409ec37b | 99 | #define CONFIG_MTD_DEVICE |
28b00324 DB |
100 | #define CONFIG_CMD_NAND |
101 | #define CONFIG_CMD_UBI | |
102 | #define CONFIG_RBTREE | |
103 | #endif | |
104 | ||
28b00324 DB |
105 | #ifdef CONFIG_USB_DAVINCI |
106 | #define CONFIG_MUSB_HCD | |
107 | #define CONFIG_CMD_USB | |
108 | #define CONFIG_USB_STORAGE | |
109 | #else | |
110 | #undef CONFIG_MUSB_HCD | |
111 | #undef CONFIG_CMD_USB | |
112 | #undef CONFIG_USB_STORAGE | |
113 | #endif | |
114 | ||
115 | #define CONFIG_CRC32_VERIFY | |
116 | #define CONFIG_MX_CYCLIC | |
117 | ||
118 | /* U-Boot general configuration */ | |
28b00324 DB |
119 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
120 | #define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */ | |
121 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
122 | #define CONFIG_SYS_PBSIZE /* Print buffer size */ \ | |
123 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
124 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
125 | #define CONFIG_SYS_HUSH_PARSER | |
28b00324 DB |
126 | #define CONFIG_SYS_LONGHELP |
127 | ||
409ec37b SP |
128 | #ifdef CONFIG_NAND_DAVINCI |
129 | #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ | |
130 | #define CONFIG_ENV_IS_IN_NAND | |
131 | #define CONFIG_ENV_OFFSET 0x3C0000 | |
132 | #undef CONFIG_ENV_IS_IN_FLASH | |
133 | #endif | |
28b00324 | 134 | |
073eacf0 SP |
135 | #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) |
136 | #define CONFIG_CMD_ENV | |
137 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ | |
138 | #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ | |
139 | #define CONFIG_ENV_IS_IN_MMC | |
140 | #undef CONFIG_ENV_IS_IN_FLASH | |
141 | #endif | |
142 | ||
409ec37b | 143 | #define CONFIG_BOOTDELAY 5 |
28b00324 DB |
144 | #define CONFIG_BOOTCOMMAND \ |
145 | "dhcp;bootm" | |
146 | #define CONFIG_BOOTARGS \ | |
147 | "console=ttyS0,115200n8 " \ | |
148 | "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" | |
149 | ||
150 | #define CONFIG_CMDLINE_EDITING | |
151 | #define CONFIG_VERSION_VARIABLE | |
152 | #define CONFIG_TIMESTAMP | |
153 | ||
154 | #define CONFIG_NET_RETRY_COUNT 10 | |
155 | ||
156 | /* U-Boot memory configuration */ | |
409ec37b | 157 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ |
28b00324 DB |
158 | #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ |
159 | #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ | |
160 | ||
161 | /* Linux interfacing */ | |
162 | #define CONFIG_CMDLINE_TAG | |
163 | #define CONFIG_SETUP_MEMORY_TAGS | |
164 | #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ | |
165 | #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ | |
166 | ||
167 | ||
168 | /* NAND configuration ... socketed with two chipselects. It normally comes | |
169 | * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other | |
170 | * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC | |
171 | * pretty much demands the 4-bit ECC support.) You can of course swap in | |
172 | * other parts, including small page ones. | |
173 | * | |
174 | * This presents a single read-only partition for all bootloader stuff. | |
175 | * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and | |
176 | * some extra space to help cope with bad blocks in that data. Linux | |
177 | * shouldn't care about its detailed layout, and will probably want to use | |
178 | * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to | |
179 | * override this default partitioning using MTDPARTS and cmdlinepart. | |
180 | */ | |
181 | #define MTDIDS_DEFAULT "nand0=davinci_nand.0" | |
182 | ||
183 | #ifdef CONFIG_SYS_NAND_LARGEPAGE | |
184 | /* Use same layout for 128K/256K blocks; allow some bad blocks */ | |
185 | #define PART_BOOT "2m(bootloader)ro," | |
186 | #else | |
187 | /* Assume 16K erase blocks; allow a few bad ones. */ | |
188 | #define PART_BOOT "512k(bootloader)ro," | |
189 | #endif | |
190 | ||
191 | #define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ | |
192 | #define PART_REST "-(filesystem)" | |
193 | ||
194 | #define MTDPARTS_DEFAULT \ | |
195 | "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST | |
196 | ||
44df860b SP |
197 | #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ |
198 | ||
199 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
200 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
201 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
202 | ||
28b00324 | 203 | #endif /* __CONFIG_H */ |