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c74b2108 SK |
1 | /* |
2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
c74b2108 SK |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
c74b2108 SK |
9 | |
10 | /*=======*/ | |
11 | /* Board */ | |
12 | /*=======*/ | |
13 | #define SCHMOOGIE | |
6d0f6bcf JCPV |
14 | #define CONFIG_SYS_NAND_LARGEPAGE |
15 | #define CONFIG_SYS_USE_NAND | |
0647508d CR |
16 | #define MACH_TYPE_SCHMOOGIE 1255 |
17 | #define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE | |
18 | ||
c74b2108 SK |
19 | /*===================*/ |
20 | /* SoC Configuration */ | |
21 | /*===================*/ | |
22 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ | |
6d0f6bcf JCPV |
23 | #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ |
24 | #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ | |
25 | #define CONFIG_SYS_HZ 1000 | |
f7904368 | 26 | #define CONFIG_SOC_DM644X |
c74b2108 SK |
27 | /*=============*/ |
28 | /* Memory Info */ | |
29 | /*=============*/ | |
6d0f6bcf | 30 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ |
6d0f6bcf JCPV |
31 | #define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */ |
32 | #define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ | |
c74b2108 | 33 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
c74b2108 SK |
34 | #define PHYS_SDRAM_1 0x80000000 /* DDR Start */ |
35 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ | |
950a3924 | 36 | #define DDR_4BANKS /* 4-bank DDR2 (128MB) */ |
c74b2108 SK |
37 | /*====================*/ |
38 | /* Serial Driver info */ | |
39 | /*====================*/ | |
6d0f6bcf JCPV |
40 | #define CONFIG_SYS_NS16550 |
41 | #define CONFIG_SYS_NS16550_SERIAL | |
7ee38c04 | 42 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */ |
6d0f6bcf | 43 | #define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ |
7239c5da | 44 | #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */ |
c74b2108 SK |
45 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
46 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
c74b2108 SK |
47 | /*===================*/ |
48 | /* I2C Configuration */ | |
49 | /*===================*/ | |
50 | #define CONFIG_HARD_I2C | |
51 | #define CONFIG_DRIVER_DAVINCI_I2C | |
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ |
53 | #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
c74b2108 SK |
54 | /*==================================*/ |
55 | /* Network & Ethernet Configuration */ | |
56 | /*==================================*/ | |
57 | #define CONFIG_DRIVER_TI_EMAC | |
58 | #define CONFIG_MII | |
59 | #define CONFIG_BOOTP_DEFAULT | |
60 | #define CONFIG_BOOTP_DNS | |
61 | #define CONFIG_BOOTP_DNS2 | |
62 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
63 | #define CONFIG_NET_RETRY_COUNT 10 | |
64 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
65 | /*=====================*/ | |
66 | /* Flash & Environment */ | |
67 | /*=====================*/ | |
5a1aceb0 | 68 | #undef CONFIG_ENV_IS_IN_FLASH |
6d0f6bcf | 69 | #define CONFIG_SYS_NO_FLASH |
ee4f3e27 | 70 | #define CONFIG_NAND_DAVINCI |
97f4eb8c | 71 | #define CONFIG_SYS_NAND_CS 2 |
51bfee19 | 72 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
0e8d1586 | 73 | #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ |
a16df2c1 | 74 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
c74b2108 | 75 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ |
6d0f6bcf JCPV |
76 | #define CONFIG_SYS_NAND_BASE 0x02000000 |
77 | #define CONFIG_SYS_NAND_HW_ECC | |
78 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
0e8d1586 | 79 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
c74b2108 SK |
80 | /*=====================*/ |
81 | /* Board related stuff */ | |
82 | /*=====================*/ | |
83 | #define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ |
c74b2108 | 85 | #define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ |
6d0f6bcf | 86 | #define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */ |
c74b2108 SK |
87 | /*==============================*/ |
88 | /* U-Boot general configuration */ | |
89 | /*==============================*/ | |
c74b2108 SK |
90 | #define CONFIG_MISC_INIT_R |
91 | #undef CONFIG_BOOTDELAY | |
92 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */ |
94 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
95 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */ | |
96 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
97 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
98 | #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ | |
c74b2108 SK |
99 | #define CONFIG_VERSION_VARIABLE |
100 | #define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_HUSH_PARSER |
c74b2108 | 102 | #define CONFIG_CMDLINE_EDITING |
6d0f6bcf | 103 | #define CONFIG_SYS_LONGHELP |
c74b2108 SK |
104 | #define CONFIG_CRC32_VERIFY |
105 | #define CONFIG_MX_CYCLIC | |
106 | /*===================*/ | |
107 | /* Linux Information */ | |
108 | /*===================*/ | |
109 | #define LINUX_BOOT_PARAM_ADDR 0x80000100 | |
110 | #define CONFIG_CMDLINE_TAG | |
111 | #define CONFIG_SETUP_MEMORY_TAGS | |
112 | #define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" | |
113 | #define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" | |
114 | /*=================*/ | |
115 | /* U-Boot commands */ | |
116 | /*=================*/ | |
117 | #include <config_cmd_default.h> | |
118 | #define CONFIG_CMD_ASKENV | |
119 | #define CONFIG_CMD_DHCP | |
120 | #define CONFIG_CMD_DIAG | |
121 | #define CONFIG_CMD_I2C | |
122 | #define CONFIG_CMD_MII | |
123 | #define CONFIG_CMD_PING | |
124 | #define CONFIG_CMD_SAVES | |
125 | #define CONFIG_CMD_DATE | |
126 | #define CONFIG_CMD_NAND | |
127 | #undef CONFIG_CMD_EEPROM | |
128 | #undef CONFIG_CMD_BDI | |
129 | #undef CONFIG_CMD_FPGA | |
130 | #undef CONFIG_CMD_SETGETDCR | |
131 | #undef CONFIG_CMD_FLASH | |
132 | #undef CONFIG_CMD_IMLS | |
11e238d6 | 133 | |
8f5d4687 HM |
134 | #ifdef CONFIG_CMD_BDI |
135 | #define CONFIG_CLOCKS | |
136 | #endif | |
137 | ||
11e238d6 SP |
138 | #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */ |
139 | ||
140 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
141 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 | |
142 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ | |
143 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
144 | GENERATED_GBL_DATA_SIZE) | |
145 | ||
c74b2108 | 146 | #endif /* __CONFIG_H */ |