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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2bae75a4 SR |
2 | /* |
3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
2bae75a4 SR |
4 | */ |
5 | ||
6 | #ifndef _CONFIG_DB_88F6820_GP_H | |
7 | #define _CONFIG_DB_88F6820_GP_H | |
8 | ||
9 | /* | |
10 | * High Level Configuration Options (easy to change) | |
11 | */ | |
2bae75a4 | 12 | |
2bae75a4 SR |
13 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
14 | ||
15 | /* | |
16 | * Commands configuration | |
17 | */ | |
2bae75a4 SR |
18 | |
19 | /* I2C */ | |
20 | #define CONFIG_SYS_I2C | |
21 | #define CONFIG_SYS_I2C_MVTWSI | |
22 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE | |
23 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
24 | #define CONFIG_SYS_I2C_SPEED 100000 | |
25 | ||
e80f1e85 SR |
26 | /* |
27 | * SDIO/MMC Card Configuration | |
28 | */ | |
e80f1e85 SR |
29 | #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE |
30 | ||
7cbaff95 SR |
31 | /* |
32 | * SATA/SCSI/AHCI configuration | |
33 | */ | |
7cbaff95 SR |
34 | #define CONFIG_SCSI_AHCI_PLAT |
35 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 | |
36 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
37 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
38 | CONFIG_SYS_SCSI_MAX_LUN) | |
39 | ||
59565736 | 40 | /* USB/EHCI configuration */ |
59565736 SR |
41 | #define CONFIG_EHCI_IS_TDI |
42 | ||
2bae75a4 | 43 | /* Environment in SPI NOR flash */ |
2bae75a4 | 44 | |
2bae75a4 SR |
45 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
46 | ||
ce2cb1d3 | 47 | /* PCIe support */ |
6451223a | 48 | #ifndef CONFIG_SPL_BUILD |
ce2cb1d3 | 49 | #define CONFIG_PCI_SCAN_SHOW |
6451223a | 50 | #endif |
ce2cb1d3 | 51 | |
3fd38af7 KS |
52 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
53 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
54 | "fdt_high=0x10000000\0" \ | |
55 | "initrd_high=0x10000000\0" | |
56 | ||
9e30b31d | 57 | /* SPL */ |
7853c508 SR |
58 | /* |
59 | * Select the boot device here | |
60 | * | |
61 | * Currently supported are: | |
62 | * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash | |
63 | * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) | |
64 | */ | |
65 | #define SPL_BOOT_SPI_NOR_FLASH 1 | |
66 | #define SPL_BOOT_SDIO_MMC_CARD 2 | |
67 | #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH | |
68 | ||
9e30b31d | 69 | /* Defines for SPL */ |
9e30b31d | 70 | #define CONFIG_SPL_SIZE (140 << 10) |
9e30b31d SR |
71 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) |
72 | ||
73 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) | |
74 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
75 | ||
6451223a SR |
76 | #ifdef CONFIG_SPL_BUILD |
77 | #define CONFIG_SYS_MALLOC_SIMPLE | |
78 | #endif | |
9e30b31d SR |
79 | |
80 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
81 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
82 | ||
7853c508 | 83 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH |
9e30b31d | 84 | /* SPL related SPI defines */ |
7853c508 SR |
85 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
86 | #endif | |
87 | ||
88 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD | |
89 | /* SPL related MMC defines */ | |
7853c508 SR |
90 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) |
91 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS | |
7853c508 SR |
92 | #ifdef CONFIG_SPL_BUILD |
93 | #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ | |
94 | #endif | |
95 | #endif | |
9e30b31d | 96 | |
2bae75a4 SR |
97 | /* |
98 | * mv-common.h should be defined after CMD configs since it used them | |
99 | * to enable certain macros | |
100 | */ | |
101 | #include "mv-common.h" | |
102 | ||
103 | #endif /* _CONFIG_DB_88F6820_GP_H */ |