[people/ms/u-boot.git] / include / configs / dbau1x00.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * This file contains the configuration parameters for the dbau1x00 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
#define CONFIG_DBAU1X00		1
#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */

#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000	1
#else
#ifdef CONFIG_DBAU1100
#define CONFIG_SOC_AU1100	1
#else
#ifdef CONFIG_DBAU1500
#define CONFIG_SOC_AU1500	1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
#define CONFIG_SOC_AU1550	1
#else
#error "No valid board set"
#endif
#endif
#endif
#endif

#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */

#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/

#define CONFIG_BAUDRATE		115200

/* valid baudrates */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"addmisc=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate} "				\
		"panic=1\0"						\
	"bootfile=/tftpboot/vmlinux.srec\0"				\
	"load=tftp 80500000 ${u-boot}\0"				\
	""

#ifdef CONFIG_DBAU1550
/* Boot from flash by default, revert to bootp */
#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
#else /* CONFIG_DBAU1550 */
#define CONFIG_BOOTCOMMAND	"bootp;bootm"
#endif /* CONFIG_DBAU1550 */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_BEDBUG
#undef CONFIG_CMD_ELF
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MII
#undef CONFIG_CMD_RUN


#ifdef CONFIG_DBAU1550

#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_NET

#undef CONFIG_CMD_I2C
#undef CONFIG_CMD_IDE
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_PCMCIA

#else

#define CONFIG_CMD_IDE
#define CONFIG_CMD_DHCP

#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

#endif


/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory      */

#define	CFG_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */

#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args*/

#define CFG_MALLOC_LEN		128*1024

#define CFG_BOOTPARAMS_LEN	128*1024

#define CFG_MHZ			396

#if (CFG_MHZ % 12) != 0
#error "Invalid CPU frequency - must be multiple of 12!"
#endif

#define CFG_MIPS_TIMER_FREQ	(CFG_MHZ * 1000000)

#define CFG_HZ			1000

#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */

#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/

#define CFG_MEMTEST_START	0x80100000
#define CFG_MEMTEST_END		0x80800000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef CONFIG_DBAU1550

#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */

#else /* CONFIG_DBAU1550 */

#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */

#endif /* CONFIG_DBAU1550 */

#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}

#define CFG_FLASH_CFI           1
#define CONFIG_FLASH_CFI_DRIVER    1

/* The following #defines are needed to get flash environment right */
#define	CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MONITOR_LEN		(192 << 10)

#define CFG_INIT_SP_OFFSET	0x400000

/* We boot from this flash, selected with dip switch */
#define CFG_FLASH_BASE		PHYS_FLASH_2

/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */

#define	CONFIG_ENV_IS_NOWHERE	1

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR		0xB0030000
#define CONFIG_ENV_SIZE		0x10000

#define CONFIG_FLASH_16BIT

#define CONFIG_NR_DRAM_BANKS	2

#define CONFIG_NET_MULTI

#ifdef CONFIG_DBAU1550
#define MEM_SIZE 192
#else
#define MEM_SIZE 64
#endif

#define CONFIG_MEMSIZE_IN_BYTES

#ifndef CONFIG_DBAU1550
/*---ATA PCMCIA ------------------------------------*/
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
#define CFG_PCMCIA_MEM_ADDR 0x20000000
#define CONFIG_PCMCIA_SLOT_A

#define CONFIG_ATAPI 1
#define CONFIG_MAC_PARTITION 1

/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1

/* We only support one slot for now */
#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET     8

/* Offset for normal register accesses  */
#define CFG_ATA_REG_OFFSET      0

/* Offset for alternate registers       */
#define CFG_ATA_ALT_OFFSET      0x0100
#endif /* CONFIG_DBAU1550 */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		16384
#define CFG_ICACHE_SIZE		16384
#define CFG_CACHELINE_SIZE	32

#endif	/* __CONFIG_H */
Commit	Line	Data
5da627a4 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* This file contains the configuration parameters for the dbau1x00 board.
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
	32	#define CONFIG_DBAU1X00 1
8bde63eb	33	#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4	34
a2663ea4	35	#ifdef CONFIG_DBAU1000
5da627a4	36	/* Also known as Merlot */
8bde63eb	37	#define CONFIG_SOC_AU1000 1
a2663ea4 WD	38	#else
a2663ea4 WD	39	#ifdef CONFIG_DBAU1100
8bde63eb	40	#define CONFIG_SOC_AU1100 1
a2663ea4 WD	41	#else
a2663ea4 WD	42	#ifdef CONFIG_DBAU1500
8bde63eb	43	#define CONFIG_SOC_AU1500 1
d4ca31c4	44	#else
ff36fd85 WD	45	#ifdef CONFIG_DBAU1550
ff36fd85 WD	46	/* Cabernet */
8bde63eb	47	#define CONFIG_SOC_AU1550 1
ff36fd85	48	#else
a2663ea4 WD	49	#error "No valid board set"
	50	#endif
	51	#endif
	52	#endif
ff36fd85	53	#endif
5da627a4	54
d4ca31c4	55	#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
5da627a4 WD	56
	57	#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
	58
	59	#define CONFIG_BAUDRATE 115200
	60
	61	/* valid baudrates */
	62	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	63
	64	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	65	#undef CONFIG_BOOTARGS
	66
	67	#define CONFIG_EXTRA_ENV_SETTINGS \
fe126d8b WD	68	"addmisc=setenv bootargs ${bootargs} " \
fe126d8b WD	69	"console=ttyS0,${baudrate} " \
5da627a4 WD	70	"panic=1\0" \
5da627a4 WD	71	"bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b	72	"load=tftp 80500000 ${u-boot}\0" \
5da627a4	73	""
ff36fd85 WD	74
	75	#ifdef CONFIG_DBAU1550
	76	/* Boot from flash by default, revert to bootp */
	77	#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85	78	#else /* CONFIG_DBAU1550 */
ad88297e	79	#define CONFIG_BOOTCOMMAND "bootp;bootm"
ff36fd85 WD	80	#endif /* CONFIG_DBAU1550 */
ff36fd85 WD	81
ab999ba1	82
80ff4f99 JL	83	/*
	84	* BOOTP options
	85	*/
	86	#define CONFIG_BOOTP_BOOTFILESIZE
	87	#define CONFIG_BOOTP_BOOTPATH
	88	#define CONFIG_BOOTP_GATEWAY
	89	#define CONFIG_BOOTP_HOSTNAME
	90
	91
ab999ba1 JL	92	/*
	93	* Command line configuration.
	94	*/
	95	#include <config_cmd_default.h>
	96
	97	#undef CONFIG_CMD_BDI
	98	#undef CONFIG_CMD_BEDBUG
	99	#undef CONFIG_CMD_ELF
	100	#undef CONFIG_CMD_ENV
	101	#undef CONFIG_CMD_FAT
	102	#undef CONFIG_CMD_FPGA
	103	#undef CONFIG_CMD_MII
	104	#undef CONFIG_CMD_RUN
	105
	106
	107	#ifdef CONFIG_DBAU1550
	108
	109	#define CONFIG_CMD_FLASH
	110	#define CONFIG_CMD_LOADB
	111	#define CONFIG_CMD_NET
	112
	113	#undef CONFIG_CMD_I2C
	114	#undef CONFIG_CMD_IDE
	115	#undef CONFIG_CMD_NFS
	116	#undef CONFIG_CMD_PCMCIA
	117
	118	#else
	119
	120	#define CONFIG_CMD_IDE
	121	#define CONFIG_CMD_DHCP
	122
	123	#undef CONFIG_CMD_FLASH
	124	#undef CONFIG_CMD_LOADB
	125	#undef CONFIG_CMD_LOADS
	126
	127	#endif
	128
5da627a4 WD	129
	130	/*
	131	* Miscellaneous configurable options
	132	*/
	133	#define CFG_LONGHELP /* undef to save memory */
ff36fd85 WD	134
	135	#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
	136
5da627a4 WD	137	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	138	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	139	#define CFG_MAXARGS 16 /* max number of command args*/
	140
	141	#define CFG_MALLOC_LEN 128*1024
	142
	143	#define CFG_BOOTPARAMS_LEN 128*1024
	144
ff36fd85 WD	145	#define CFG_MHZ 396
	146
	147	#if (CFG_MHZ % 12) != 0
	148	#error "Invalid CPU frequency - must be multiple of 12!"
	149	#endif
	150
a55d4817 SK	151	#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000)
	152
	153	#define CFG_HZ 1000
5da627a4 WD	154
	155	#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
	156
	157	#define CFG_LOAD_ADDR 0x81000000 /* default load address */
	158
	159	#define CFG_MEMTEST_START 0x80100000
	160	#define CFG_MEMTEST_END 0x80800000
	161
	162	/*-----------------------------------------------------------------------
	163	* FLASH and environment organization
	164	*/
ff36fd85 WD	165	#ifdef CONFIG_DBAU1550
	166
	167	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	168	#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
	169
	170	#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
	171	#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
	172
ff36fd85 WD	173	#else /* CONFIG_DBAU1550 */
ff36fd85 WD	174
5da627a4 WD	175	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	176	#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
	177
	178	#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
	179	#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
	180
ff36fd85 WD	181	#endif /* CONFIG_DBAU1550 */
ff36fd85 WD	182
ad88297e HS	183	#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e HS	184
ff36fd85	185	#define CFG_FLASH_CFI 1
00b1883a	186	#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85	187
5da627a4 WD	188	/* The following #defines are needed to get flash environment right */
	189	#define CFG_MONITOR_BASE TEXT_BASE
	190	#define CFG_MONITOR_LEN (192 << 10)
	191
	192	#define CFG_INIT_SP_OFFSET 0x400000
	193
	194	/* We boot from this flash, selected with dip switch */
	195	#define CFG_FLASH_BASE PHYS_FLASH_2
	196
	197	/* timeout values are in ticks */
	198	#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
	199	#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
	200
93f6d725	201	#define CONFIG_ENV_IS_NOWHERE 1
5da627a4 WD	202
5da627a4 WD	203	/* Address and size of Primary Environment Sector */
0e8d1586 JCPV	204	#define CONFIG_ENV_ADDR 0xB0030000
0e8d1586 JCPV	205	#define CONFIG_ENV_SIZE 0x10000
5da627a4 WD	206
	207	#define CONFIG_FLASH_16BIT
	208
	209	#define CONFIG_NR_DRAM_BANKS 2
	210
	211	#define CONFIG_NET_MULTI
	212
ff36fd85 WD	213	#ifdef CONFIG_DBAU1550
	214	#define MEM_SIZE 192
	215	#else
	216	#define MEM_SIZE 64
	217	#endif
	218
5da627a4 WD	219	#define CONFIG_MEMSIZE_IN_BYTES
5da627a4 WD	220
ff36fd85	221	#ifndef CONFIG_DBAU1550
5da627a4 WD	222	/---ATA PCMCIA ------------------------------------/
	223	#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
	224	#define CFG_PCMCIA_MEM_ADDR 0x20000000
	225	#define CONFIG_PCMCIA_SLOT_A
	226
	227	#define CONFIG_ATAPI 1
	228	#define CONFIG_MAC_PARTITION 1
	229
	230	/* We run CF in "true ide" mode or a harddrive via pcmcia */
	231	#define CONFIG_IDE_PCMCIA 1
	232
	233	/* We only support one slot for now */
	234	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	235	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	236
	237	#undef CONFIG_IDE_LED /* LED for ide not supported */
	238	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	239
	240	#define CFG_ATA_IDE0_OFFSET 0x0000
	241
	242	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
	243
d4ca31c4	244	/* Offset for data I/O */
5da627a4 WD	245	#define CFG_ATA_DATA_OFFSET 8
	246
	247	/* Offset for normal register accesses */
	248	#define CFG_ATA_REG_OFFSET 0
	249
	250	/* Offset for alternate registers */
	251	#define CFG_ATA_ALT_OFFSET 0x0100
ff36fd85	252	#endif /* CONFIG_DBAU1550 */
5da627a4 WD	253
	254	/*-----------------------------------------------------------------------
	255	* Cache Configuration
	256	*/
	257	#define CFG_DCACHE_SIZE 16384
	258	#define CFG_ICACHE_SIZE 16384
	259	#define CFG_CACHELINE_SIZE 32
	260
5da627a4	261	#endif /* __CONFIG_H */