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Commit | Line | Data |
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5da627a4 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5da627a4 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * This file contains the configuration parameters for the dbau1x00 board. | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
5da627a4 | 15 | #define CONFIG_DBAU1X00 1 |
8bde63eb | 16 | #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ |
5da627a4 | 17 | |
74368693 DS |
18 | #define CONFIG_DISPLAY_BOARDINFO |
19 | ||
a2663ea4 | 20 | #ifdef CONFIG_DBAU1000 |
5da627a4 | 21 | /* Also known as Merlot */ |
8bde63eb | 22 | #define CONFIG_SOC_AU1000 1 |
a2663ea4 WD |
23 | #else |
24 | #ifdef CONFIG_DBAU1100 | |
8bde63eb | 25 | #define CONFIG_SOC_AU1100 1 |
a2663ea4 WD |
26 | #else |
27 | #ifdef CONFIG_DBAU1500 | |
8bde63eb | 28 | #define CONFIG_SOC_AU1500 1 |
d4ca31c4 | 29 | #else |
ff36fd85 WD |
30 | #ifdef CONFIG_DBAU1550 |
31 | /* Cabernet */ | |
8bde63eb | 32 | #define CONFIG_SOC_AU1550 1 |
ff36fd85 | 33 | #else |
a2663ea4 WD |
34 | #error "No valid board set" |
35 | #endif | |
36 | #endif | |
37 | #endif | |
ff36fd85 | 38 | #endif |
5da627a4 | 39 | |
5da627a4 WD |
40 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
41 | ||
42 | #define CONFIG_BAUDRATE 115200 | |
43 | ||
44 | /* valid baudrates */ | |
5da627a4 WD |
45 | |
46 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
47 | #undef CONFIG_BOOTARGS | |
48 | ||
49 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
fe126d8b WD |
50 | "addmisc=setenv bootargs ${bootargs} " \ |
51 | "console=ttyS0,${baudrate} " \ | |
5da627a4 WD |
52 | "panic=1\0" \ |
53 | "bootfile=/tftpboot/vmlinux.srec\0" \ | |
fe126d8b | 54 | "load=tftp 80500000 ${u-boot}\0" \ |
5da627a4 | 55 | "" |
ff36fd85 WD |
56 | |
57 | #ifdef CONFIG_DBAU1550 | |
58 | /* Boot from flash by default, revert to bootp */ | |
59 | #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" | |
ff36fd85 | 60 | #else /* CONFIG_DBAU1550 */ |
ad88297e | 61 | #define CONFIG_BOOTCOMMAND "bootp;bootm" |
ff36fd85 WD |
62 | #endif /* CONFIG_DBAU1550 */ |
63 | ||
ab999ba1 | 64 | |
80ff4f99 JL |
65 | /* |
66 | * BOOTP options | |
67 | */ | |
68 | #define CONFIG_BOOTP_BOOTFILESIZE | |
69 | #define CONFIG_BOOTP_BOOTPATH | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | ||
73 | ||
ab999ba1 JL |
74 | /* |
75 | * Command line configuration. | |
76 | */ | |
ab999ba1 | 77 | #undef CONFIG_CMD_BEDBUG |
ab999ba1 | 78 | #undef CONFIG_CMD_FAT |
ab999ba1 | 79 | #undef CONFIG_CMD_MII |
ab999ba1 JL |
80 | |
81 | #ifdef CONFIG_DBAU1550 | |
82 | ||
ab999ba1 | 83 | #undef CONFIG_CMD_IDE |
ab999ba1 JL |
84 | #undef CONFIG_CMD_PCMCIA |
85 | ||
86 | #else | |
87 | ||
88 | #define CONFIG_CMD_IDE | |
ab999ba1 | 89 | |
ab999ba1 JL |
90 | #endif |
91 | ||
5da627a4 WD |
92 | |
93 | /* | |
94 | * Miscellaneous configurable options | |
95 | */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
ff36fd85 | 97 | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
99 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
100 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
5da627a4 | 101 | |
6d0f6bcf | 102 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
5da627a4 | 103 | |
6d0f6bcf | 104 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
5da627a4 | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_MHZ 396 |
ff36fd85 | 107 | |
6d0f6bcf | 108 | #if (CONFIG_SYS_MHZ % 12) != 0 |
ff36fd85 WD |
109 | #error "Invalid CPU frequency - must be multiple of 12!" |
110 | #endif | |
111 | ||
6d0f6bcf | 112 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) |
a55d4817 | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ |
5da627a4 | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ |
5da627a4 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MEMTEST_START 0x80100000 |
119 | #define CONFIG_SYS_MEMTEST_END 0x80800000 | |
5da627a4 WD |
120 | |
121 | /*----------------------------------------------------------------------- | |
122 | * FLASH and environment organization | |
123 | */ | |
ff36fd85 WD |
124 | #ifdef CONFIG_DBAU1550 |
125 | ||
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
127 | #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ | |
ff36fd85 WD |
128 | |
129 | #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ | |
130 | #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ | |
131 | ||
ff36fd85 WD |
132 | #else /* CONFIG_DBAU1550 */ |
133 | ||
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
135 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
5da627a4 WD |
136 | |
137 | #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ | |
138 | #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ | |
139 | ||
ff36fd85 WD |
140 | #endif /* CONFIG_DBAU1550 */ |
141 | ||
6d0f6bcf | 142 | #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} |
ad88297e | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 145 | #define CONFIG_FLASH_CFI_DRIVER 1 |
ff36fd85 | 146 | |
5da627a4 | 147 | /* The following #defines are needed to get flash environment right */ |
9a893d24 MY |
148 | /* ROM version */ |
149 | #define CONFIG_SYS_TEXT_BASE 0xbfc00000 | |
150 | /* RAM version */ | |
151 | /* #define CONFIG_SYS_TEXT_BASE 0x80100000 */ | |
152 | ||
14d0a02a | 153 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) |
5da627a4 | 155 | |
6d0f6bcf | 156 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
5da627a4 WD |
157 | |
158 | /* We boot from this flash, selected with dip switch */ | |
6d0f6bcf | 159 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 |
5da627a4 WD |
160 | |
161 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
163 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
5da627a4 | 164 | |
93f6d725 | 165 | #define CONFIG_ENV_IS_NOWHERE 1 |
5da627a4 WD |
166 | |
167 | /* Address and size of Primary Environment Sector */ | |
0e8d1586 JCPV |
168 | #define CONFIG_ENV_ADDR 0xB0030000 |
169 | #define CONFIG_ENV_SIZE 0x10000 | |
5da627a4 WD |
170 | |
171 | #define CONFIG_FLASH_16BIT | |
172 | ||
173 | #define CONFIG_NR_DRAM_BANKS 2 | |
174 | ||
5da627a4 | 175 | |
ff36fd85 WD |
176 | #ifdef CONFIG_DBAU1550 |
177 | #define MEM_SIZE 192 | |
178 | #else | |
179 | #define MEM_SIZE 64 | |
180 | #endif | |
181 | ||
5da627a4 WD |
182 | #define CONFIG_MEMSIZE_IN_BYTES |
183 | ||
ff36fd85 | 184 | #ifndef CONFIG_DBAU1550 |
5da627a4 | 185 | /*---ATA PCMCIA ------------------------------------*/ |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ |
187 | #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 | |
5da627a4 WD |
188 | #define CONFIG_PCMCIA_SLOT_A |
189 | ||
190 | #define CONFIG_ATAPI 1 | |
191 | #define CONFIG_MAC_PARTITION 1 | |
192 | ||
193 | /* We run CF in "true ide" mode or a harddrive via pcmcia */ | |
194 | #define CONFIG_IDE_PCMCIA 1 | |
195 | ||
196 | /* We only support one slot for now */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
198 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
5da627a4 WD |
199 | |
200 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
201 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
202 | ||
6d0f6bcf | 203 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
5da627a4 | 204 | |
6d0f6bcf | 205 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
5da627a4 | 206 | |
d4ca31c4 | 207 | /* Offset for data I/O */ |
6d0f6bcf | 208 | #define CONFIG_SYS_ATA_DATA_OFFSET 8 |
5da627a4 WD |
209 | |
210 | /* Offset for normal register accesses */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_ATA_REG_OFFSET 0 |
5da627a4 WD |
212 | |
213 | /* Offset for alternate registers */ | |
6d0f6bcf | 214 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
ff36fd85 | 215 | #endif /* CONFIG_DBAU1550 */ |
5da627a4 WD |
216 | |
217 | /*----------------------------------------------------------------------- | |
218 | * Cache Configuration | |
219 | */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
221 | #define CONFIG_SYS_ICACHE_SIZE 16384 | |
222 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
5da627a4 | 223 | |
5da627a4 | 224 | #endif /* __CONFIG_H */ |